Datasheet

AD9481
Rev. 0 | Page 13 of 28
75
70
65
60
55
50
45
40
0 300
SFDR
SNR
SINAD
25020015010050
05045-010
SAMPLE CLOCK (MHz)
(dB)
Figure 10. SNR, SINAD, SFDR vs. Sample Clock Frequency,
A
IN
= 70 MHz @ −1 dB
80
70
60
50
40
30
20
10
0
–70 0–10–20–30–40–50–60
05045-011
ANALOG INPUT DRIVE LEVEL (dBFS)
(dB)
SFDR (dBFS)
SFDR (dBc)
60dB
REFERENCE LINE
Figure 11. SFDR vs. A
IN
Input Level; A
IN
= 70 MHz @ 250 MSPS
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
0408020 60 100 120
05045-012
(MHz)
(dB)
F1, F2 = –7dBFS
2F2–F1 = –65.9dBc
2F1–F2 = –64.9dBc
Figure 12. Two-Tone Intermodulation Distortion
(69.3 MHz and 70.3 MHz; f
S
= 250 MSPS)
0
140
I
AVDD
I
DRVDD
120
100
80
60
40
20
0 100 20050 150 250 300
05045-013
SAMPLE CLOCK (MSPS)
CURRENT (mA)
Figure 13. I
AVDD
and I
DRVDD
vs. Clock Rate, C
LOAD
= 5 pF
A
IN
= 70 MHz @ −1 dBFS
40
50
49
48
47
46
45
44
43
42
41
20 40 6030 50 70 80
05045-014
CLOCK POSITIVE DUTY CYCLE (%)
(dB)
DCS ON
DCS OFF
Figure 14. SNR, SINAD vs. Clock Pulse-Width High,
A
IN
= 70 MHz @ −1 dBFS, 250 MSPS, DCS On/Off
40.0
50.0
47.5
45.0
42.5
55
75
70
65
60
0.5 1.10.9 1.50.7 1.3 1.7 1.9
05045-015
EXTERNAL VREF VOLTAGE (V)
SNR, SINAD (dB)
SFDR (dBc)
SNR
SINAD
SFDR
Figure 15. SNR, SINAD, and SFDR vs. VREF in External Reference Mode, A
IN
=
70 MHz @ −1 dBFS, 250 MSPS