Datasheet

AD9480
Rev. A | Page 6 of 28
SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, differential clock input, DCS enabled, unless otherwise noted.
Table 4.
AD9480-250
Parameter Temp Test Level Min Typ Max Unit
CLOCK
Maximum Conversion Rate Full VI 250 MSPS
Minimum Conversion Rate Full VI 20 MSPS
Clock Pulse Width High (t
EH
) Full IV 1.2 2 ns
Clock Pulse Width Low (t
EL
) Full IV 1.2 2 ns
OUTPUT PARAMETERS
Valid Time (t
V
)
1
Full VI 1.9 ns
Propagation Delay (t
PD
) Full VI 2.8 3.8 ns
Rise Time (t
R
) 20% to 80% Full V 0.5 ns
Fall Time (t
F
) 20% to 80% Full V 0.5 ns
DCO Propagation Delay (t
CPD
) Full VI 1.9 2.7 3.7 ns
Data-to-DCO Skew (t
PD
− t
CPD
) Full IV 0 0.1 0.6 ns
Pipeline Latency 25°C VI 8 Cycles
APERTURE
Aperture Delay (t
A
) 25°C V 1.5 ns
Aperture Uncertainty (Jitter) 25°C V 0.25 ps rms
1
Valid time is approximately equal to minimum t
PD
. C
LOAD
equals 5 pF maximum.
TIMING DIAGRAM
N–1
N
N+1
N+8
N+9
N+10
N+11
t
EH
t
EL
1/f
S
t
A
N–8
t
PD
8 CYCLES
t
V
N–7 N N+1 N+2
t
CPD
CLK+
CLK–
DATA
OUT
DCO–
DCO+
AIN
04619-002
Figure 2. Timing Diagram