Datasheet

AD9480
Rev. A | Page 13 of 28
TEMPERATURE ( ° C)
GAIN ERROR (%)
3
2
0
1
–1
–2
–3
–40 0–20 20 40 60 80
04619-032
FS = 1V EXT REF
FS = 1V INT REF
Figure 16. Full-Scale Gain Error vs. Temperature,
A
IN
= 70.3 MHz @ −0.5 dBFS, 250 MSPS, FS = 1
TEMPERATURE (°C)
dB
75
65
70
60
45
50
55
40
–40 –20 2004060
04619-033
80
SFDR 1V INT REF
SINAD 1V INT REF
Figure 17. SINAD, SFDR vs. Temperature, A
IN
= 70 MHz @ −1 dBFS, 250 MSPS
AVDD (V)
CHANGE IN VREF (%)
0.10
0
0.05
–0.15
–0.10
–0.05
2.7 2.8 2.9 3.1 3.53.43.33.23.0 3.6
04619-034
Figure 18. VREF Sensitivity to AVDD
SINAD
AVDD (V)
dB
70
65
60
55
50
45
3.0 3.1 3.2 3.3 3.4 3.5 3.6
04619-035
SFDR
SNR
Figure 19. SNR, SINAD, and SFDR vs. Supply Voltage,
A
IN
= 70.3 MHz @ −1 dBFS, 250 MSPS
CODE
LSB
0.5
0.3
0.4
0
0.1
0.2
–0.2
–0.1
–0.5
–0.3
–0.4
0 10050 150 200 250
04619-036
Figure 20. Typical DNL Plot, A
IN
= 10.3 MHz @ –0.5 dBFS, 250 MSPS
CODE
LSB
0.50
0.25
0
–0.50
–0.25
0 10050 150 200 250
04619-037
Figure 21. Typical INL Plot, A
IN
= 10.3 MHz @ −0.5 dBFS, 250 MSPS