Datasheet

AD9480
Rev. A | Page 12 of 28
SFDR
SNR
SINAD
SAMPLE CLOCK (MHz)
dB
75
70
65
60
55
50
45
40
0 50 150 200100 250 300
04619-026
Figure 10. SNR, SINAD, SFDR vs. Sample Clock Frequency, A
IN
= 70 MHz @ −1 dBFS
ANALOG INPUT DRIVE LEVEL (dBFS)
dB
80
60
70
40
50
20
30
0
10
–70 –60 –40–50 –30 –20 –10 0
04619-027
SFDRdBFS
SFDRdBc
65dB
REF LINE
Figure 11. SFDR vs. A
IN
Input Level; A
IN
= 70 MHz @ 250 MSPS
MHz
dB
0
–20
–10
–50
–40
–30
–70
–60
–90
–80
0604020 80 100 120
04619-028
F1, F2 = –7dBFS
2F2-F1 = –71.1dBc
2F1-F2 = –68dBc
Figure 12. Two-Tone Intermodulation Distortion
(69.3 MHz and 70.3 MHz; f
S
= 250 MSPS)
ENCODE (MSPS)
CURRENT IN mA
180
160
100
120
140
60
40
20
80
0
0 50 100 200 250150 300
04619-029
I
AVDD
I
DRVDD
Figure 13. I
AVDD
and I
DRVDD
vs. Clock Rate, C
LOAD
= 5 pF A
IN
= 70 MHz @ –1 dBFS
DCS OFF
DCS ON
CLOCK POSITIVE DUTY CYCLE (%)
dB
50
49
48
47
46
45
43
42
41
44
40
20 30 40 50 60 70 80
046190-030
Figure 14. SNR, SINAD vs. Clock Pulse Width High,
A
IN
= 70 MHz @ –1 dBFS, 250 MSPS, DCS On/Off
EXTERNAL VREF VOLTAGE (V)
SNR, SINAD dB
50.0
47.5
45.0
42.5
40.0
0.5 1.10.90.7 1.51.3 1.7 1.9
04619-031
SNR
SFDR
50
65
70
75
80
SFDR dB
SINAD
Figure 15. SNR, SINAD, and SFDR vs. VREF in External Reference Mode,
A
IN
= 70 MHz @ –1 dBFS, 250 MSPS