Datasheet

AD9444
Rev. 0 | Page 7 of 40
N+1
N+2
N–1
t
CLKL
12 CYCLES
05089-003
N
t
CLKH
t
PD
VIN
CLK+
CLK–
DX
DCO+
DCO–
t
DCOPD
N-12 N-11 N-1 N
Figure 3. CMOS Timing Diagram
EXPLANATION OF TEST LEVELS
Test Level Definitions
I 100% production tested.
II 100% production tested at 25°C and sample tested at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.