Datasheet

AD9444
Rev. 0 | Page 6 of 40
SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4.
AD9444BSVZ-80
Parameter Temp Test Level
Min Typ Max
Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate Full VI 80 MSPS
Minimum Conversion Rate Full V 10 MSPS
CLK Period Full V 12.5 ns
CLK Pulse Width High
1
(t
CLKH
) Full V 4 ns
CLK Pulse Width Low
1
(t
CLKL
) Full V 4 ns
DATA OUTPUT PARAMETERS
Output Propagation Delay—CMOS (t
PD
)
2
(DX, DCO+) Full IV 3 5.25 8 ns
Output Propagation Delay—LVDS (t
PD
)
3
(DX+, DCO+) Full VI 3 5 7.5 ns
Pipeline Delay (Latency) Full V 12 Cycles
Aperture Delay (t
A
) Full V ns
Aperture Uncertainty (Jitter, t
J
) Full V 0.2 ps rms
1
With duty cycle stabilizer (DCS) enabled.
2
Output propagation delay is measured from clock 50% transition to data 50% transition, with 5 pF load.
3
LVDS R
TERM
= 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
N–12
N–11
N
N+1
A
IN
CLK+
CLK–
DATA OUT
DCO+
DCO–
N
N+1
N–1
t
CLKH
t
CLKL
1/f
S
t
PD
12 CLOCK CYCLES
t
CPD
05089-002
Figure 2. LVDS Mode Timing Diagram