Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TQFP 100 EP

14-Bit, 80 MSPS, A/D Converter

AD9444

Rev. 0

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However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

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FEATURES

80 MSPS guaranteed sampling rate

100 dB two-tone SFDR with 69.3 MHz and 70.3 MHz

73.1 dB SNR with 70 MHz input

97 dBc SFDR with 70 MHz input

Excellent linearity

DNL = ±0.4 LSB typical

INL = ±0.6 LSB typical

1.2 W power dissipation

3.3 V and 5 V supply operation

2.0 V p-p differential full-scale input

LVDS outputs (ANSI-644 compatible)

Data format select

Output clock available

APPLICATIONS

Multicarrier, multimode cellular receivers

Antenna array positioning

Power amplifier linearization

Broadband wireless

Radar, infared imaging

Communications instrumentation

GENERAL DESCRIPTION

The AD9444 is a 14-bit monolithic, sampling analog-to-digital

converter (ADC) with an on-chip, track-and-hold circuit and is

optimized for power, small size, and ease of use. The product

operates at up to an 80 MSPS conversion rate and is optimized

for multicarrier, multimode receivers, such as those found in

cellular infrastructure equipment.

The ADC requires 3.3 V and 5.0 V power supplies and a low

voltage differential input clock for full performance operation.

No external reference or driver components are required for

many applications. Data outputs are LVDS-compatible (ANSI-

644) or CMOS-compatible and include the means to reduce

the overall current needed for short trace distances.

FUNCTIONAL BLOCK DIAGRAM

CMOS

LVDS

OUTPUT

STAGING

CLOCK

AND TIMING

MANAGEMENT

AGND DRGND DRVDD

VREF

CLK+

VIN+

AD9444

VIN–

CLK–

DCO

05089-001

AVDD1 AVDD2

DCS MODE

DFS

OUTPUT MODE

T/H

BUFFER

PIPELINE

ADC

D13–D0

REF

REFBSENSE REFT

Figure 1.

Optional features allow users to implement various selectable

operating conditions, including data format select and output

data mode.

The AD9444 is available in a 100-lead surface-mount plastic

package (100-lead TQFP/EP) specified over the industrial

temperature range (−40°C to +85°C).

PRODUCT HIGHLIGHTS

1. High performance: Outstanding SFDR performance for mul-

ticarrier, multimode 3G and 4G cellular base station

receivers.

2. Ease of use: On-chip reference and track-and-hold. An

output clock simplifies data capture.

3. Packaged in a Pb-free, 100-lead TQFP/EP.

4. Clock DCS maintains overall ADC performance over a wide

range of clock pulse widths.

5. OR (out-of-range) outputs indicate when the signal is beyond

the selected input range.

Summary of content (40 pages)

PAGE 1
4-Bit, 80 MSPS, A/D Converter AD9444 FEATURES APPLICATIONS Multicarrier, multimode cellular receivers Antenna array positioning Power amplifier linearization Broadband wireless Radar, infared imaging Communications instrumentation GENERAL DESCRIPTION The AD9444 is a 14-bit monolithic, sampling analog-to-digital converter (ADC) with an on-chip, track-and-hold circuit and is optimized for power, small size, and ease of use.
PAGE 2
AD9444 TABLE OF CONTENTS DC Specifications ............................................................................. 3 Clock Input Considerations...................................................... 22 AC Specifications.............................................................................. 4 Power Considerations................................................................ 23 Digital Specifications........................................................................ 5 Digital Outputs .
PAGE 3
AD9444 DC SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed reference (1.0 V mode), AIN = −0.5 dBFS, DCS on, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error1 Differential Nonlinearity (DNL)2 Integral Nonlinearity (INL)2 TEMPERATURE DRIFT Offset Error Gain Error VOLTAGE REFERENCE Output Voltage1 Load Regulation @ 1.0 mA Reference Input Current (External 1.
PAGE 4
AD9444 AC SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed reference (1.0 V mode), AIN = −0.5 dBFS, DCS on, unless otherwise noted. Table 2.
PAGE 5
AD9444 DIGITAL SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDSBIAS = 3.74 kΩ, unless otherwise noted. Table 3. Parameter CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance DIGITAL OUTPUT BITS—CMOS Mode (D0 to D13, OTR)1 DRVDD = 3.
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AD9444 SWITCHING SPECIFICATIONS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted. Table 4.
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AD9444 N N–1 N+1 VIN N+2 tCLKL tCLKH CLK– CLK+ tPD 12 CYCLES N-12 DX N-11 N-1 N tDCOPD 05089-003 DCO+ DCO– Figure 3. CMOS Timing Diagram EXPLANATION OF TEST LEVELS Test Level I II III IV V VI Definitions 100% production tested. 100% production tested at 25°C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only.
PAGE 8
AD9444 ABSOLUTE MAXIMUM RATINGS Thermal Resistance Table 5. With Respect to Parameter ELECTRICAL AVDD1 AGND AVDD2 AGND DRVDD DGND AGND DGND AVDD1 DRVDD AVDD2 DRVDD AVDD2 AVDD1 D0 to D13 DGND CLK, MODE AGND VIN+, VIN− AGND VREF AGND SENSE AGND REFT, REFB AGND ENVIRONMENTAL Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature Min Max Unit −0.3 −0.3 −0.3 −0.3 −4 −4 −4 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 +4 +6 +4 +0.3 +4 +6 +6 DRVDD + 0.3 AVDD1 + 0.
PAGE 9
AD9444 DEFINITIONS OF SPECIFICATIONS Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Aperture Delay (tA) The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled.
PAGE 10
AD9444 76 D11– 78 D12– 77 D11+ 79 D12+ 81 D13+ (MSB) 80 D13– 82 DRGND 83 DRVDD 84 OR– 86 AGND 85 OR+ 87 AVDD1 88 AGND 89 AVDD1 91 AVDD1 90 AVDD1 92 AVDD1 93 AVDD1 94 AVDD1 96 AGND 95 AVDD1 97 AGND 99 AGND 98 AVDD1 100 DCS MODE PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AVDD1 1 75 DRVDD DNC 2 74 DRGND DNC 3 DNC 4 73 D10+ 72 D10– OUTPUT MODE 5 DFS 6 71 D9+ 70 D9– LVDSBIAS 7 69 D8+ AVDD1 8 AVDD1 9 68 D8– 67 DRGND 66 D7+ 65 D7– SENSE 10 VREF 11 AD9444 AGND
PAGE 11
AD9444 Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode Pin No. 1, 8 to 9, 16 to 18, 24 to 27, 34 to 35, 38, 41 to 42, 87, 89 to 95, 98 2 to 4 Mnemonic AVDD1 Description 3.3 V (±5%) Analog Supply. DNC 5 OUTPUT MODE 6 DFS 7 LVDSBIAS 10 SENSE 11 VREF 12, 15, 20, 23, 32, 86, 88, 96 to 97, 99, Exposed Heat Sink 13 AGND Do Not Connect. These pins should float. CMOS Compatible Output Logic Mode Control Pin.
PAGE 12
76 D7 78 D9 77 D8 79 D10 81 D12 80 D11 82 DRGND 83 DRVDD 84 D13 (MSB) 86 AGND 85 OR 87 AVDD1 88 AGND 89 AVDD1 91 AVDD1 90 AVDD1 92 AVDD1 93 AVDD1 96 AGND 95 AVDD1 94 AVDD1 98 AVDD1 97 AGND 100 DCS MODE 99 AGND AD9444 AVDD1 1 75 DRVDD DNC 2 74 DRGND DNC 3 DNC 4 73 D6 72 D5 OUTPUT MODE 5 DFS 6 71 D4 70 D3 DNC 7 69 D2 AVDD1 8 AVDD1 9 68 D1 67 DRGND 66 D0 (LSB) 65 DNC SENSE 10 VREF 11 AD9444 AGND 12 64 DCO+ TOP VIEW (Not to Scale) REFT 13 REFB 14 63 DCO– 62 D
PAGE 13
AD9444 Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode Pin No. 1, 8 to 9, 16 to 18, 24 to 27, 34 to 35, 38, 41 to 42, 87, 89 to 95, 98 2 to 4, 7, 43 to 46, 49 to 52, 55 to 60, 65 5 Mnemonic AVDD1 Description 3.3 V (±5%) Analog Supply. DNC Do Not Connect. These pins should float. OUTPUT MODE 10 SENSE 11 VREF 12, 15, 20, 23, 32, 86, 88, 96 to 97, 99, Exposed Heat Sink 13 AGND 14 REFB 19, 28 to 31, 39 to 40 21 22 AVDD2 CMOS Compatible Output Logic Mode Control Pin.
PAGE 14
AD9444 EQUIVALENT CIRCUITS AVDD2 VIN+ AVDD2 DRVDD 1kΩ 2.5pF DX 3.5V AVDD2 05089-009 SHA X1 1kΩ Figure 9. Equivalent CMOS Digital Output Circuit 05089-006 VIN– 2.5pF VDD Figure 6. Equivalent Analog Input Circuit DRVDD DRVDD DCS MODE, OUTPUT MODE, DFS 30kΩ K LVDSBIAS 3.74kΩ ILVDSOUT 05089-007 05089-010 1.2V Figure 10. Equivalent Digital Input Circuit, DFS, DCS MODE, OUTPUT MODE Figure 7.
PAGE 15
AD9444 TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, sample rate = 80 MSPS, LVDS mode, DCS enabled, TA = 25°C, 2 V p-p differential input, AIN = −0.5 dBFS, internal trimmed reference (nominal VREF = 1.0 V), unless otherwise noted. 0 80MSPS 100.3MHz @ –0.5dBFS SNR: 72.3dB ENOB: 11.
PAGE 16
AD9444 75 75 SNR dB @ –40°C 74 74 SNR dB @ –40°C 73 73 SNR dB @ +25°C 72 SNR dB @ +85°C (dB) (dB) SNR dB @ +25°C 71 71 70 70 69 69 68 68 67 67 66 66 0 20 40 60 80 100 120 140 160 ANALOG INPUT FREQUENCY (MHz) 180 65 05089-018 65 200 SNR dB @ +85°C 0 20 40 60 80 100 120 140 160 180 05089-021 72 200 ANALOG INPUT FREQUENCY (MHz) Figure 18. SNR vs. Analog Input Frequency, 80 MSPS/LVDS Mode Figure 21. SNR vs.
PAGE 17
AD9444 0 0 SFDR: 102dBFS –10 90dBFS REFERENCE LINE –20 –20 AMPLITUDE (dBFS) –30 –40 SFDR (dBc) IMD (dBFS) –40 –60 –50 –60 –70 –80 –80 –100 –100 WORST THIRD-ORDER IMD (dBc) –90 SFDR (dBFS) –110 5 10 15 20 25 30 35 40 FREQUENCY (MHz) –120 –110 –100 –90 0 0 –10 90dBFS REFERENCE LINE –20 –20 –30 –30 –50 –60 –70 –80 –40 SFDR (dBc) –50 –60 –70 WORST THIRD-ORDER IMD (dBc) –80 SFDR (dBFS) –90 –100 –100 –110 –110 –120 –120 –110 –100 –90 5 10 15 20 25 30 35 4
PAGE 18
AD9444 0 12000 61.44MSPS TOTAL INPUT SIGNAL POWER: –30dBFS –10 –20 10000 –30 AMPLITUDE (dBFS) –40 8000 FREQUENCY –50 –60 –70 –80 6000 4000 –90 –100 2000 –110 0 7.68 15.36 FREQUENCY (MHz) 23.04 30.72 0 05089-030 –130 8179 8180 8181 8182 8183 BIN 8184 8185 8186 8187 05089-033 –120 Figure 33. Ground Input Histogram 80 MSPS, VIN+ = VIN−, 32K Samples Figure 30. 64K FFT, 61.44 MSPS, 4 @ WCDMA, IF = 46.08 MHz 250 0 NPR: 63.1dB –10 230 –20 210 190 –40 AVDD1 (3.
PAGE 19
AD9444 0.961 0.2 0.960 0.1 0 0.958 0.957 GAIN (%FS) REFERENCE VOLTAGE (V) 0.959 0.956 0.955 0.954 –0.1 –0.2 –0.3 0.953 0 20 40 TEMPERATURE (°C) 60 80 –0.5 –40 –20 0.75 0.50 0.50 INL ERROR (LSB) 0.75 0.25 0 –0.25 –0.25 –0.75 –0.75 6144 8192 10240 12288 14336 16384 OUTPUT CODE 80 0 –0.50 4096 60 0.25 –0.50 05089-037 DNL ERROR (LSB) 1.00 2048 40 Figure 38. Gain vs. Temperature 1.00 0 20 TEMPERATURE (°C) Figure 36. VREF vs. Temperature –1.00 0 Figure 37.
PAGE 20
AD9444 THEORY OF OPERATION The AD9444 architecture is optimized for high speed and ease of use. The analog inputs drive an integrated, high bandwidth, track-and-hold circuit that samples the signal prior to quantization by the 14-bit pipeline ADC core. The device includes an on-board reference and input logic that accepts TTL, CMOS, or LVPECL levels. The digital output logic levels are user selectable as standard 3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT MODE pin.
PAGE 21
AD9444 Table 9. Reference Configuration Summary Selected Mode External Reference Internal Fixed Reference Programmable Reference SENSE Voltage AVDD VREF 0.2 V to VREF Resulting VREF (V) N/A 0.5 Internal Fixed Reference AGND to 0.2 V 1.0 Resulting Differential Span (V p-p) 2 × External Reference 1.0 2 × VREF R2 ⎞ ⎛ 0.5 × ⎜ 1 + ⎟ (See Figure 41) R1 ⎠ ⎝ 2.0 External Reference Operation Analog Inputs As with most new high speed, high dynamic range ADCs, the analog input to the AD9444 is differential.
PAGE 22
AD9444 Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to the clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9444 contains a clock duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle.
PAGE 23
AD9444 75 tion resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. LVDS mode facilitates interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor as close to the receiver as possible.
PAGE 24
AD9444 Table 10. Digital Output Coding Code 16383 8192 8191 0 VIN+ − VIN− Input Span = 2 V p-p (V) 1.000 0 −0.000122 −1.00 VIN+ − VIN− Input Span = 1 V p-p (V) 0.500 0 −0.000061 −0.
PAGE 25
Rev. 0 | Page 25 of 40 Figure 47. LVDS Mode Evaluation Board Schematic C13 20pF GND VCC VCC VCC 5V GND VCC VCC GND GND U1 PIN DEFINITIONS LVDS/CMOS AD9444 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 C9 0.1µF C91 0.1µF GND R13 xx C51 10µF ANALOG R6 36Ω R4 36Ω C2 0.1µF GND TOUTB GND R28 33Ω C5 TINB E15 0.1µF C12 0.1µF 0.
PAGE 26
AD9444 POWER OPTIONS ADP3338 PJ-102A C33 10µF GND 5V VIN 3 + C34 10µF C4 10µF C89 10µF 05089-051 GND GND GND 2 OUT1 OUT IN + 1 + C6 10µF GND 5V 4 C88 10µF 1 3 GND + 1 GND VIN 3 5V DRVDD DRVDD OUT1 OUT GND U14 IN + GND GND GND ADP3338 2 VCC VCC + U3 1 3 2 C87 10µF ADP3338 GND 2 3 C1 10µF + 4 OUT1 OUT IN C57 10µF 3.3V 2 VIN 3 + + 1 GND 4 GND IN 2 VIN OUT1 OUT 1 VDL VDL GND 4 VIN P4 3.3V GND U15 3.
PAGE 27
AD9444 U7 SN75LVDS386 P6 C40MS 39 37 GND DOR_C/D13_YN D13_C/D11_YN D12_C/D9_YN D11_C/D7_YN D10_C/D5_YN D9_C/D3_YN D8_C/D1_YN D7_CN DRBN D6_CN D5_CN D4_CN D3_CN D2_CN 35 33 31 P39 P40 P37 P38 P35 P36 P33 P32 P29 P30 P27 P28 25 P25 23 P23 P26 21 P21 19 P19 P22 17 P17 15 P15 P18 13 P13 11 P11 P14 9 P9 7 P7 P10 29 27 D0_CN 5 P5 3 P3 GND 1 P1 D1_CN 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 GND P34 P31 2 P24 P20 P16 P12 P8 P6 P4 P2 40 GND 38 36 34 GND DOR_T/D
PAGE 28
05089-057 05089-060 AD9444 Figure 54. LVDS Mode Evaluation Board Layout, Ground Plane 2 05089-061 05089-058 Figure 51. LVDS Mode Evaluation Board Layout, Primary Side 05089-059 05089-062 Figure 55. LVDS Mode Evaluation Board Layout, Power Plane 1 Figure 52. LVDS Mode Evaluation Board Layout, Secondary Side Figure 56. LVDS Mode Evaluation Board Layout, Power Plane 2 Figure 53. LVDS Mode Evaluation Board Layout, Ground Plane 1 Rev.
PAGE 29
05089-063 05089-064 AD9444 Figure 57. LVDS Mode Evaluation Board Layout, Primary Silkscreen Figure 58. LVDS Mode Evaluation Board Layout, Secondary Silkscreen Rev.
PAGE 30
AD9444 LVDS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) Table 11. Item 1 2 Qty.
PAGE 31
AD9444 Item 26 Qty. 24 27 28 29 1 2 1 30 1 31 5 1 REFDES C10, C11, C13, to C19, C29, C31, C36 to C38, C45, C49, C59, C62, C69, C70 to C73, C901 J51 P5, P61 R1, R2, R5, R7, R131 R17 to R20, R27, R36 to R38, R401 U21 Description Capacitors, Select 10 V Ceramic X5R 0402 Manufacturer Panasonic MFG_PART_NO Connector, Gold, Male, Coaxial, SMA, Vertical Power Connectors Resistors, Select 1/16 W 1% 0402 SMD Johnston Comp.
PAGE 32
Rev. 0 | Page 32 of 40 Figure 59. CMOS Mode Evaluation Board Schematic E15 TOUTB GND R6 36Ω R4 36Ω C9 0.1µF C91 0.
PAGE 33
AD9444 ADP3338 U8 U15 3 1 VIN VIN 1 GND GND VCC C6 10µF + C33 10µF GND GND 5V OUT1 IN 1 2 3 + C4 10µF Figure 60. CMOS Mode Evaluation Board Schematic (Continued) Rev. 0 | Page 33 of 40 05089-055 C89 10µF GND + GND GND OUT C34 10µF + C88 10µF 3 2 VIN 3 GND 4 VIN IN 2 5V DRVDD DRVDD OUT1 GND U14 OUT 3 GND GND GND ADP3338 U3 1 2 C87 10µF ADP3338 GND 2 + + 3.
PAGE 34
AD9444 40 RZ1 220 RSO16ISO DORC/D13Y D13T/D12Y D13C/D11Y D12T/D10Y D12C/D9Y D11T/D8Y D11C/D7Y R1 16 2 R2 15 3 R3 14 4 R4 13 5 R5 12 6 R6 11 7 R7 10 8 R8 9 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 XOR2IN GND VDL GND RZ2 220 RSO16ISO D10T/D6Y D10C/D5Y D9T/D4Y D9C/D3Y D8T/D2Y D8C/D1Y D7T/D0Y 1 R1 16 2 R2 15 3 R3 14 4 R4 13 5 R5 12 6 R6 11 7 R7 10 8 R8 9 GND VDL GND XOR2IN 38 R1 36 1 Q = OUTPUT LE2 D = INPUT OE2 2Q8 2D
PAGE 35
05089-065 05089-068 AD9444 05089-066 05089-069 Figure 65. CMOS Mode Evaluation Board Layout, Ground Plane 2 Figure 62. CMOS Mode Evaluation Board Layout, Primary Side 05089-067 05089-070 Figure 66. CMOS Mode Evaluation Board Layout, Power Plane 1 Figure 63. CMOS Mode Evaluation Board Layout, Secondary Side Figure 67. CMOS Mode Evaluation Board Layout, Power Plane 2 Figure 64. CMOS Mode Evaluation Board Layout, Ground Plane 1 Rev.
PAGE 36
05089-071 05089-072 AD9444 Figure 68. CMOS Mode Evaluation Board Layout, Primary Silkscreen Figure 69. CMOS Mode Evaluation Board Layout, Secondary Silkscreen Rev.
PAGE 37
AD9444 CMOS MODE EVALUATION BOARD BILL OF MATERIALS (BOM) Table 12. Item 1 2 Qty. 1 16 REFDES AD9444PCB C1, C4, C6, C33, C34, C39, C44, C55 to C57, C64 to C66, C87 to C89 Description PCB, AD9444 LVDS Evaluation Board Capacitors, Tantalum, SMT BCAPTAJC, 10 µF, 16 V, 10% Manufacturer PCSM KEMET MFG_PART_NO AD9444LVDSCUSTREVC T491C106K016AS 3 32 C2, C3, C5, C9, C12, C20 to C23, C26 to C28, C30, C32, C35, C40, C42, C43, C46 to C48, C50, C52, C53, C58, C60, C61, C75, C78, C85, C91, C92 Capacitors, 0.
PAGE 38
AD9444 Item 26 Qty. 26 27 28 1 15 29 30 31 32 3 1 1 2 1 REFDES C10, C11, C13, C14 to C19, C29, C31, C36 to C37, C38, C45, C49, C59, C62,C69, C70 to C73, C90, C93, C961 J51 R1,R2,R5,R7, R13, R17 to R20, R27, R36 to R401 R16, R41, R421 C631 U41 P5, P61 Description Capacitors, Select 10 V Ceramic X5R 0402 Manufacturer Panasonic MFG_PART_NO Connector, Gold, Male, Coaxial, SMA, Vertical Resistors, Select 1/16 W 1% 0402 SMD Johnston Comp.
PAGE 39
AD9444 OUTLINE DIMENSIONS 0.75 0.60 0.45 16.00 SQ 1.20 MAX 14.00 SQ 100 1 76 76 75 100 1 75 SEATING PLANE BOTTOM VIEW (PINS UP) TOP VIEW (PINS DOWN) CONDUCTIVE HEAT SINK 51 25 26 0.20 0.09 51 50 25 50 1.05 1.00 0.95 7° 3.5° 0° 0.50 BSC 0.27 0.22 0.17 0.15 0.05 26 6.50 NOM COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MS-026AED-HD NOTES 1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED. 2.