Datasheet

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12-Bit, 80 MSPS/105 MSPS ADC

AD9432

Rev. F

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FEATURES

On-chip reference and track-and-hold

On-chip input buffer

Power dissipation: 850 mW typical at 105 MSPS

500 MHz analog bandwidth

SNR: 67 dB @ 49 MHz AIN at 105 MSPS

SFDR: 80 dB @ 49 MHz AIN at 105 MSPS

2.0 V p-p analog input range

5.0 V supply operation

3.3 V CMOS/TTL outputs

Twos complement output format

APPLICATIONS

Communications

Base stations and zero-IF subsystems

Wireless local loop (WLL)

Local multipoint distribution service (LMDS)

HDTV broadcast cameras and film scanners

GENERAL INTRODUCTION

The AD9432 is a 12-bit, monolithic sampling analog-to-digital

converter (ADC) with an on-chip track-and-hold circuit and is

optimized for high speed conversion and ease of use. The prod-

uct operates up to a 105 MSPS conversion rate with outstanding

dynamic performance over its full operating range.

The ADC requires only a single 5.0 V power supply and a 105 MHz

encode clock for full performance operation. No external refer-

ence or driver components are required for many applications.

The digital outputs are TTL-/CMOS-compatible, and a separate

output power supply pin supports interfacing with 3.3 V logic.

The encode input supports either differential or single-ended

mode and is TTL-/CMOS-compatible.

Fabricated on an advanced BiCMOS process, the AD9432 is

available in a 52-lead low profile quad flat package (LQFP) and

in a 52-lead thin quad flat package (TQFP_EP). The AD9432 is

specified over the industrial temperature range of −40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

T/HBUF

PIPELINE

ADC

REF

TIMING

OUTPUT

STAGING

AD9432

GND VREFOUT VREFIN

D11 TO D0

ENCODE

AIN

00587-001

Figure 1.

Summary of content (16 pages)

PAGE 1
2-Bit, 80 MSPS/105 MSPS ADC AD9432 FEATURES GENERAL INTRODUCTION On-chip reference and track-and-hold On-chip input buffer Power dissipation: 850 mW typical at 105 MSPS 500 MHz analog bandwidth SNR: 67 dB @ 49 MHz AIN at 105 MSPS SFDR: 80 dB @ 49 MHz AIN at 105 MSPS 2.0 V p-p analog input range 5.0 V supply operation 3.
PAGE 2
AD9432 TABLE OF CONTENTS Features .............................................................................................. 1 Terminology .................................................................................... 11 Applications ....................................................................................... 1 Equivalent Circuits ......................................................................... 12 General Introduction ........................................................
PAGE 3
AD9432 SPECIFICATIONS VDD = 3.3 V, VCC = 5.0 V; external reference; differential encode input, unless otherwise noted. Table 1.
PAGE 4
AD9432 Parameter POWER SUPPLY Power Dissipation 3 IVCC IVDD Power Supply Rejection Ratio (PSRR) DYNAMIC PERFORMANCE 4 Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 10 MHz fIN = 40 MHz fIN = 49 MHz fIN = 70 MHz Signal-to-Noise and Distortion (SINAD) Ratio (with Harmonics) fIN = 10 MHz fIN = 40 MHz fIN = 49 MHz fIN = 70 MHz Effective Number of Bits (ENOB) fIN = 10 MHz fIN = 40 MHz fIN = 49 MHz fIN = 70 MHz Second-Order and Third-Order Harmonic Distortion fIN = 10 MHz fIN = 40 MHz fIN = 49 MHz fIN = 70
PAGE 5
AD9432 TIMING DIAGRAM SAMPLE N – 1 SAMPLE N SAMPLE N + 10 SAMPLE N + 11 AIN tA SAMPLE N + 1 tEH tEL SAMPLE N + 9 1/fS ENCODE ENCODE D11 TO D0 DATA N – 11 DATA N – 10 DATA N–9 DATA N–2 DATA N – 1 Figure 2. Timing Diagram Rev.
PAGE 6
AD9432 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 2. Parameter VDD VCC Analog Inputs Digital Inputs VREFIN Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature Table 3 lists AD9432 thermal characteristics for simulated typical performance in a 4-layer JEDEC board, horizontal orientation. Rating 6V 6V −0.5 V to VCC + 0.5 V −0.5 V to VDD + 0.5 V −0.5 V to VCC + 0.
PAGE 7
AD9432 VCC 2 PIN 1 GND DNC VCC GND VCC VREFIN VREFOUT VCC GND AIN GND 1 39 GND VCC 2 38 GND GND 3 39 GND PIN 1 38 GND 37 VCC GND 3 37 VCC GND 4 GND 4 36 VCC VCC 5 AD9432 VCC 5 VCC 6 VCC 6 TOP VIEW (Not to Scale) ENCODE 7 ENCODE 8 32 VDD GND 9 31 DGND AD9432 35 GND TOP VIEW (Not to Scale) 34 GND ENCODE 33 GND ENCODE 8 36 VCC 7 35 GND 34 GND 33 GND 32 VDD GND 9 31 DGND VCC 10 30 D0 (LSB) GND 11 29 D1 GND 11 29 D1 DGND 12 28 D2 DGND 12 28 D2 VDD
PAGE 8
AD9432 TYPICAL PERFORMANCE CHARACTERISTICS 70 90 AIN = –0.5dBFS AIN = 10.3MHz 85 65 80 SNR (dB) SNR/SINAD/SFDR (dB) SFDR 75 70 SNR 60 55 SINAD 60 0 20 40 60 80 100 120 140 50 160 00587-012 00587-009 65 0 50 100 150 200 250 ANALOG INPUT FREQUENCY (MHz) ENCODE (MSPS) Figure 5. SNR/SINAD/SFDR vs. fS, fIN = 10.3 MHz Figure 8. SNR vs. fIN, Encode = 105 MSPS 100 –50 AIN = 10.3MHz ENCODE = 105MSPS –55 90 –60 HARMONICS (dBc) –70 –75 –80 –85 80 2ND or 3RD (–6.
PAGE 9
AD9432 0 ENCODE = 105MSPS AIN = 10.3MHz (–0.53dBFS) SNR = 67.32dB SINAD = 67.07dB SFDR = –85dBc –20 –20 AMPLITUDE (dBFS) –30 –40 –50 –60 –70 –80 –50 –60 –70 –80 –90 –100 –100 –110 –120 –110 –120 FREQUENCY FREQUENCY Figure 11. FFT: fS = 105 MSPS, fIN = 10.3 MHz Figure 14. FFT: fS = 105 MSPS, fIN = 50.3 MHz 0 0 –20 –60 –70 –80 –40 –50 –60 –70 –80 –90 –90 –100 –100 –120 –110 –120 FREQUENCY FREQUENCY Figure 12. FFT: fS = 105 MSPS, fIN = 27 MHz Figure 15.
PAGE 10
AD9432 1.00 100 0.75 dBFS 90 0.50 80 ENCODE = 105MSPS AIN = 50.3MHz 0.25 INL (LSB) 70 60 50 dBc 0 40 –0.25 30 –0.50 20 –70 –60 –50 –40 –30 –20 –10 00587-023 10 0 –80 –0.75 00587-021 WORST-CASE SPURIOUS (dBc and dBFS) 110 –1.00 0 ANALOG INPUT POWER LEVEL (dBFS) Figure 19. Integral Nonlinearity, fS = 105 MSPS Figure 17. Single-Tone SFDR, fS = 105 MSPS, fIN = 50.3 MHz 1.00 3.0 0.75 0.50 2.5 VOLTAGE (V) 0 –0.25 2.0 –0.75 –1.00 00587-024 –0.50 00587-022 DNL (LSB) 0.
PAGE 11
AD9432 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels. Aperture Delay The delay between a differential crossing of ENCODE and ENCODE and the instant at which the analog input is sampled.
PAGE 12
AD9432 EQUIVALENT CIRCUITS VDD VCC VREFIN 00587-004 00587-007 Dx Figure 24. Digital Output Circuit Figure 21. Voltage Reference Input Circuit VCC VCC 5kΩ 5kΩ 7kΩ 7kΩ AIN VREFOUT 00587-008 00587-005 AIN Figure 25. Analog Input Circuit Figure 22. Voltage Reference Output Circuit VCC 17kΩ 17kΩ 100Ω 100Ω ENCODE ENCODE 8kΩ 00587-006 8kΩ Figure 23. Encode Input Circuit Rev.
PAGE 13
AD9432 THEORY OF OPERATION The AD9432 is a 12-bit pipeline converter that uses a switchedcapacitor architecture. Optimized for high speed, this converter provides flat dynamic performance up to frequencies near Nyquist. DNL transitional errors are calibrated at final test to a typical accuracy of 0.25 LSB or less. Note that the encode inputs cannot be driven directly from PECL level signals (VIHD is 3.5 V maximum). PECL level signals can easily be accommodated by ac coupling, as shown in Figure 27.
PAGE 14
AD9432 DIGITAL OUTPUTS VOLTAGE REFERENCE The digital outputs are 3.3 V (2.7 V to 3.6 V) TTL-/CMOScompatible for lower power consumption. The output data format is twos complement (see Table 6). A stable and accurate 2.5 V voltage reference is built into the AD9432 (VREFOUT). In normal operation, the internal reference is used by strapping Pin 45 to Pin 46 and placing a 0.1 μF decoupling capacitor at VREFIN. Table 6. Twos Complement Output Coding (VREF = 2.5 V) Code +2047 … 0 −1 … −2048 AIN − AIN (V) 1.
PAGE 15
AD9432 APPLICATIONS INFORMATION 66 USING THE AD8138 TO DRIVE THE AD9432 The AD8138 differential output op amp can be used to drive the AD9432 in dc-coupled applications. The AD8138 was specifically designed for ADC driver applications. Superior SNR performance is maintained up to analog frequencies of 30 MHz. The AD8138 op amp provides single-ended-to-differential conversion, which allows for a low cost alternative to transformer coupling for ac applications, as well.
PAGE 16
AD9432 OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 52 40 39 1 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 0.20 0.09 7° 3.5° 0° SEATING PLANE 13 27 14 0.10 COPLANARITY VIEW A VIEW A 26 0.38 0.32 0.22 0.65 BSC LEAD PITCH 051706-A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCC Figure 32. 52-Lead Low Profile Quad Flat Package [LQFP] (ST-52) Dimensions shown in millimeters 1.20 MAX 12.00 BSC SQ 52 0.15 0.05 0.20 0.09 7° 3.5° 0° 0.