Datasheet

AD9430
Rev. E | Page 9 of 44
TIMING DIAGRAMS
PORT A
DA11–DA0
PORT B
DB11–DB0
PARALLEL DATA OUT
PORT A
DA11–DA0
PORT B
DB11–DB0
CLK+
CLK–
DS+
DS–
INTERLEAVED DATA OUT
STATIC
STATIC
STATIC
STATIC
STATIC
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
t
SDS
14 CYCLES
t
PD
t
V
N N+2
N+3
N+1
N N+2
N+1 N+3
t
CPD
t
HDS
DCO+
DCO–
02607-002
Figure 2. CMOS Timing Diagram
N–14
N–13
N
N+1
A
IN
CLK+
CLK–
DATA OUT
DCO+
DCO–
N
N+1
N
–
1
t
EH
t
EL
1/f
S
t
PD
14 CYCLES
t
CPD
02607-003
Figure 3. LVDS Timing Diagram