Datasheet

AD9430
Rev. E | Page 8 of 44
SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, T
MIN
= –40°C, T
MAX
= +85°C, unless otherwise noted.
Table 4.
Test AD9430-170 AD9430-210
Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Unit
Maximum Conversion Rate
1
Full VI 170 210 MSPS
Minimum Conversion Rate
1
Full V 40 40 MSPS
CLK+ Pulse Width High (t
EH
)
1
Full IV 2 12.5 2 12.5 ns
CLK+ Pulse Width Low (t
EL
)
1
Full IV 2 12.5 2 12.5 ns
DS Input Setup Time (t
SDS
)
2
Full IV –0.5 –0.5 ns
DS Input Hold Time (t
HDS
)
2
Full IV 1.75 1.75 ns
OUTPUT (CMOS Mode)
Valid Time (t
V
) Full IV 2 2 ns
Propagation Delay (t
PD
) Full IV 3.8 5 3.8 5 ns
Rise Time (t
R
) (20% to 80%) 25°C V 1 1 ns
Fall Time (t
F
) (20% to 80%) 25°C V 1 1 ns
DCO Propagation Delay (t
CPD
) Full IV 3.8 5 3.8 5 ns
Data to DCO Skew (t
PD
to t
CPD
) Full IV –0.5 0 +0.5 –0.5 0 +0.5 ns
Interleaved Mode (A, B Latency) Full IV 14, 14 14, 14 Cycles
Parallel Mode (A, B Latency) Full IV 15, 14 15, 14 Cycles
OUTPUT (LVDS Mode)
Valid Time (t
V
) Full VI 2.0 2.0 ns
Propagation Delay (t
PD
) Full VI 3.2 4.3 3.2 4.3 ns
Rise Time (t
R
) (20% to 80%) 25°C V 0.5 0.5 ns
Fall Time (t
F
) (20% to 80%) 25°C V 0.5 0.5 ns
DCO Propagation Delay (t
CPD
) Full VI 1.8 2.7 3.8 1.8 2.7 3.8 ns
Data to DCO Skew (t
PD
– t
CPD
) Full IV 0.2 0.5 0.8 0.2 0.5 0.8 ns
Latency Full IV 14 14 Cycles
APERTURE DELAY (t
A
) 25°C V 1.2 1.2 ns
APERTURE UNCERTAINTY (Jitter, t
J
) 25°C V 0.25 0.25 ps rms
OUT OF RANGE RECOVERY TIME (CMOS and LVDS) 25°C V 1 1 Cycles
1
All ac specifications tested by differentially driving CLK+ and CLK−.
2
DS inputs used in CMOS mode only.