Datasheet

AD9430
Rev. E | Page 7 of 44
DIGITAL SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, T
MIN
= –40°C, T
MAX
= +85°C, unless otherwise noted.
Table 3.
Test AD9430-170 AD9430-210
Parameter Temp Level Min Typ Max Min Typ Max Unit
ENCODE AND DS INPUTS
(CLK+, CLK–, DS+, DS–)
1
Differential Input Voltage
2
Full IV 0.2 0.2 V
Common-Mode Voltage
3
Full VI 1.375 1.5 1.575 1.375 1.5 1.575 V
Input Resistance Full VI 3.2 5.5 6.5 3.2 5.5 6.5 kΩ
Input Capacitance 25°C V 4 4 pF
LOGIC INPUTS (S1, S2, S4, S5)
Logic 1 Voltage Full IV 2.0 2.0 V
Logic 0 Voltage Full IV 0.8 0.8 V
Logic 1 Input Current Full VI 190 190 μA
Logic 0 Input Current Full VI 10 10 μA
Input Resistance 25°C V 30 30 kΩ
Input Capacitance 25°C V 4 4 pF
LOGIC OUTPUTS (CMOS Mode)
Logic 1 Voltage
4
Full IV DRVDD DRVDD V
–0.05 –0.05
Logic 0 Voltage
4
Full IV 0.05 0.05 V
LOGIC OUTPUTS (LVDS Mode)
4, 5
V
OD
Differential Output Voltage Full VI 247 454 247 454 mV
V
OS
Output Offset Voltage Full VI 1.125 1.375 1.125 1.375 V
Output Coding Twos complement or binary Twos complement or binary
1
ENCODE (Clock) and DS inputs identical on the chip. See the section. Equivalent Circuits
2
All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+) – (CLK–)| > 200 mV.
3
ENCODE (Clock) inputs’ common-mode can be externally set, such that 0.9 V < (CLK+ or CLK−) < 2.6 V.
4
Digital output logic levels: DRVDD = 3.3 V, C
LOAD
= 5 pF.
5
LVDS R
TERM
= 100 Ω, LVDS output current set resistor (R
SET
) = 3.74 kΩ (1% tolerance).