Datasheet

AD9430
Rev. E | Page 19 of 44
ANALOG SUPPLY
CURRENT CMOS
MODE
ANALOG SUPPLY
CURRENT LVDS
MODE
OUTPUT SUPPLY
CURRENT LVDS
MODE
OUTPUT SUPPLY
CURRENT CMOS
MODE
ENCODE (MSPS)
100 220140 160 180 200120
I
AVDD
(ANALOG SUPPLY CURRENT) (mA)
400
0
350
50
250
150
300
200
100
I
DRVDD
(OUTPUT SUPPLY CURRENT) (mA)
80
60
40
20
0
02607-030
Figure 30. I
AVDD
and I
DRVDD
vs. Clock Rate (A
IN
= 10.3 MHz @ –0.5 dBFS)
170 MSPS Grade, C
LOAD
= 5 pF
ENCODE (MSPS)
I
AVDD
(ANALOG SUPPLY CURRENT) (mA)
I
DRVDD
(OUTPUT SUPPLY CURRENT) (mA)
450
400
350
300
250
200
150
100
50
0
90
80
70
60
50
40
30
20
10
0
100 140 160 200
220
240
120 180
ANALOG SUPPLY
CURRENT LVDS MODE
OUTPUT SUPPLY
CURRENT LVDS MODE
OUTPUT SUPPLY
CURRENT CMOS MODE
ANALOG SUPPLY
CURRENT CMOS MODE
02607-031
Figure 31. I
AVDD
and I
DRVDD
vs. Clock Rate
(A
IN
= 10.3 MHz @ –0.5 dBFS), 210 MSPS Grade, C
LOAD
= 5 pF
SINAD
SNR
SFDR
ENCODE POSITIVE DUTY CYCLE (%)
10 60 9020 40 50 70 8030
dB
85
50
80
75
70
65
60
55
02607-032
Figure 32. SINAD and SFDR vs. Clock Pulse Width High
(A
IN
= 10.3 MHz @ –0.5 dBFS, 170 MSPS, LVDS)
ENCODE POSITIVE DUTY CYCLE (%)
dB
80
75
70
65
60
55
50
20 40 50 7030 60 80
SINAD
SNR
SFDR
02607-033
Figure 33. SNR, SINAD, and SFDR vs. ENCODE Pulse Width High,
(A
IN
= 10.3 MHz @ –0.5 dBFS, 210 MSPS, LVDS)
I
LOAD
(mA)
081472
V
REFOUT
(V)
1.4
0
1.2
1.0
0.8
0.6
0.4
0.2
R
O
= 13 Ω TYP
02607-034
536
Figure 34. V
REFOUT
vs. I
LOAD
TEMPERATURE (°C)
–50 10 95–30 –10 30 50 70 90
GAIN ERROR (%)
–2.0
1.5
–1.0
1.0
0.5
0
–0.5
–1.5
% GAIN ERROR
USING EXT REF
2.0
02607-035
Figure 35. Full-Scale Gain Error vs. Temperature
(A
IN
= 10.3 MHz @ –0.5 dBFS, 170 MSPS/210 MSPS, LVDS)