Datasheet

AD9430
Rev. E | Page 14 of 44
Pin Number Mnemonic Description
22 VIN– Analog Input—Complement.
32 GND Data Sync (Input)—Not Used in LVDS Mode. Tie to GND.
36 CLK+ Clock Input—True (LVPECL Levels).
37 CLK– Clock Input—Complement (LVPECL Levels).
47, 54, 62, 75, 83 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).
48, 53, 61, 67, 74, 82 DRGND
1
Digital Output Ground.
49 D0– D0 Complement Output Bit (LSB).
50 D0+ D0 True Output Bit (LSB).
51 D1– D1 Complement Output Bit.
52 D1+ D1 True Output Bit.
55 D2– D2 Complement Output Bit.
56 D2+ D2 True Output Bit.
57 D3– D3 Complement Output Bit.
58 D3+ D3 True Output Bit.
59 D4– D4 Complement Output Bit.
60 D4+ D4 True Output Bit.
63 DCO– Data Clock Output—Complement.
64 DCO+ Data Clock Output—True.
65 D5– D5 Complement Output Bit.
66 D5+ D5 True Output Bit.
68 D6– D6 Complement Output Bit.
69 D6+ D6 True Output Bit.
70 D7– D7 Complement Output Bit.
71 D7+ D7 True Output Bit.
72 D8– D8 Complement Output Bit.
73 D8+ D8 True Output Bit.
76 D9– D9 Complement Output Bit.
77 D9+ D9 True Output Bit.
78 D10– D10 Complement Output Bit.
79 D10+ D10 True Output Bit.
80 D11– D11 Complement Output Bit.
81 D11+ D11 True Output Bit.
84 OR– Overrange Complement Output Bit.
85 OR+ Overrange True Output Bit.
1
AGND and DRGND should be tied together to a common ground plane.
2
Pin 33 can be tied to AVDD (as recommended) or left floating with no ill effects