Datasheet

AD9430
Rev. E | Page 12 of 44
Pin Number Mnemonic Description
36 CLK+ Clock Input—True.
37 CLK– Clock Input—Complement.
44 DB0 B Port Output Data Bit (LSB).
45 DB1 B Port Output Data Bit.
46 DB2 B Port Output Data Bit.
47, 54, 62, 75, 83 DRVDD 3.3 V Digital Output Supply (3.0 V to 3.6 V).
48, 53, 61, 67, 74, 82 DRGND
1
Digital Output Ground.
49 DB3 B Port Output Data Bit.
50 DB4 B Port Output Data Bit.
51 DB5 B Port Output Data Bit.
52 DB6 B Port Output Data Bit.
55 DB7 B Port Output Data Bit.
56 DB8 B Port Output Data Bit.
57 DB9 B Port Output Data Bit.
58 DB10 B Port Output Data Bit.
59 DB11 B Port Output Data Bit (MSB).
60 OR_B B Port Overrange.
63 DCO– Data Clock Output—Complement.
64 DCO+ Data Clock Output—True.
69 DA0 A Port Output Data Bit (LSB).
70 DA1 A Port Output Data Bit.
71 DA2 A Port Output Data Bit.
72 DA3 A Port Output Data Bit.
73 DA4 A Port Output Data Bit.
76 DA5 A Port Output Data Bit.
77 DA6 A Port Output Data Bit.
78 DA7 A Port Output Data Bit.
79 DA8 A Port Output Data Bit.
80 DA9 A Port Output Data Bit.
81 DA10 A Port Output Data Bit.
84 DA11 A Port Output Data Bit (MSB).
85 OR_A A Port Overrange.
1
AGND and DRGND should be tied together to a common ground plane.
2
DS Complement (DS−); can be tied to AVDD (as recommended) or left floating with no ill effects.