Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TQFP 100 EP

12-Bit, 170/210 MSPS

3.3 V A/D Converter

AD9430

Rev. E

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FEATURES

SNR = 65 dB @ f

= 70 MHz @ 210 MSPS

ENOB of 10.6 @ f

= 70 MHz @ 210 MSPS (–0.5 dBFS)

SFDR = 80 dBc @ f

= 70 MHz @ 210 MSPS (–0.5 dBFS)

Excellent linearity:

DNL = ±0.3 LSB (typical)

INL = ±0.5 LSB (typical)

2 output data options:

Demultiplexed 3.3 V CMOS outputs each @ 105 MSPS

Interleaved or parallel data output option

LVDS at 210 MSPS

700 MHz full-power analog bandwidth

On-chip reference and track-and-hold

Power dissipation = 1.3 W typical @ 210 MSPS

1.5 V input voltage range

3.3 V supply operation

Output data format option

Data sync input and data clock output provided

Clock duty cycle stabilizer

GENERAL DESCRIPTION

The AD9430 is a 12-bit, monolithic, sampling analog-to-digital

converter (ADC) optimized for high performance, low power,

and ease of use. The product operates up to a 210 MSPS

conversion rate and is optimized for outstanding dynamic

performance in wideband carrier and broadband systems. All

necessary functions, including a track-and-hold (T/H) and

reference, are included on the chip to provide a complete

conversion solution.

The ADC requires a 3.3 V power supply and a differential

ENCODE clock for full performance operation. The digital

outputs are TTL/CMOS or LVDS compatible and support either

twos complement or offset binary format. Separate output

power supply pins support interfacing with 3.3 V CMOS logic.

Two output buses support demultiplexed data up to 105 MSPS

rates in CMOS mode. A data sync input is supported for proper

output data port alignment in CMOS mode, and a data clock

output is available for proper output data timing. In LVDS

mode, the chip provides data at the ENCODE clock rate.

Fabricated on an advanced BiCMOS process, the AD9430 is

available in a 100-lead, surface-mount plastic package

(100 e-PAD TQFP) specified over the industrial temperature

range (–40°C to +85°C).

FUNCTIONAL BLOCK DIAGRAM

TRACK-

AND-HOLD

SCALABLE

REFERENCE

ADC

12-BIT

PIPELINE

CORE

LVDS

OUTPUTS

CLOCK

MANAGEMENT

SENSE VREF

AGND

DRGND

DRVDD

AVDD

DATA,

OVERRANGE

IN LVDS OR

2-PORT CMOS

DCO–

S5S4S2S1

CLK+

DS+

VIN+

AD9430

VIN–

DS–

CLK–

DCO+

SELECT CMOS

OR LVDS

CMOS

OUTPUTS

02607-001

Figure 1.

APPLICATIONS

Wireless and wired broadband communications

Cable reverse path

Communications test equipment

Radar and satellite subsystems

Power amplifier linearization

PRODUCT HIGHLIGHTS

1. High performance.

Maintains 65 dB SNR @ 210 MSPS with a 65 MHz input.

2. Low power.

Consumes only 1.3 W @ 210 MSPS.

3. Ease of use.

LVDS output data and output clock signal allow interface

to current FPGA technology. The on-chip reference and

sample-and-hold provide flexibility in system design. Use

of a single 3.3 V supply simplifies system power supply

design.

4. Out of range (OR) feature.

The OR output bit indicates when the input signal is

beyond the selected input range.

5. Pin compatible with 10-bit AD9411 (LVDS only).

Summary of content (44 pages)

PAGE 1
2-Bit, 170/210 MSPS 3.3 V A/D Converter AD9430 FUNCTIONAL BLOCK DIAGRAM FEATURES SENSE VREF AGND DRGND DRVDD AVDD AD9430 SCALABLE REFERENCE VIN+ TRACKAND-HOLD VIN– ADC 12-BIT PIPELINE CORE LVDS OUTPUTS 12 CMOS OUTPUTS DS+ DS– CLK+ SELECT CMOS OR LVDS CLOCK MANAGEMENT DCO– S1 S2 S4 S5 Figure 1. APPLICATIONS The AD9430 is a 12-bit, monolithic, sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use.
PAGE 2
AD9430 TABLE OF CONTENTS DC Specifications ............................................................................. 4 Analog Inputs ............................................................................. 28 AC Specifications.............................................................................. 6 Gain.............................................................................................. 28 Digital Specifications....................................................................
PAGE 3
AD9430 REVISION HISTORY 9/10—Rev. D to Rev. E Change to General Description Section.........................................1 Change to Operating Temperature Range Parameter, Table 5..10 Change to Figure 4 ..........................................................................11 Change to Figure 5 ..........................................................................13 Added Exposed Pad Notation to Outline Dimensions ..............42 8/05—Rev. C to Rev. D Change to IVREF Spec Units ..................
PAGE 4
AD9430 DC SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, LVDS output mode, unless otherwise noted. Table 1.
PAGE 5
AD9430 AD9430-170 Parameter POWER SUPPLY (CMOS Mode) AVDD DRVDD Supply Currents IAVDD (AVDD = 3.3 V) 5 IDRVDD (DRVDD = 3.3 V)5 Power Dissipation5 Power Supply Rejection AD9430-210 Temp Test Level Min Typ Max Min Typ Max Unit Full Full IV IV 3.1 3.0 3.3 3.3 3.6 3.6 3.2 3.0 3.3 3.3 3.6 3.6 V V Full Full Full 25°C IV IV IV V 335 24 1.1 –7.5 372 30 390 30 1.3 –7.5 450 30 mA mA W mV/V 1 Internal reference mode; SENSE = Floats.
PAGE 6
AD9430 AC SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, LVDS output mode, unless otherwise noted. 1 Table 2. Parameter SNR Analog Input @ –0.5 dBFS SINAD Analog Input @ –0.5 dBFS AD9430-170 Typ Max Min AD9430-210 Typ Max Temp Test Level Min Unit 10 MHz 70 MHz 100 MHz 240 MHz 25°C 25°C 25°C 25°C I I V V 63.5 63 65 65 65 61 62.5 62.5 64.5 64.5 64.
PAGE 7
AD9430 DIGITAL SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted. Table 3. Parameter ENCODE AND DS INPUTS (CLK+, CLK–, DS+, DS–) 1 Differential Input Voltage 2 Common-Mode Voltage 3 Input Resistance Input Capacitance LOGIC INPUTS (S1, S2, S4, S5) Logic 1 Voltage Logic 0 Voltage Logic 1 Input Current Logic 0 Input Current Input Resistance Input Capacitance LOGIC OUTPUTS (CMOS Mode) Logic 1 Voltage 4 Temp Test Level Full Full Full 25°C IV VI VI V 0.2 1.375 3.
PAGE 8
AD9430 SWITCHING SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted. Table 4.
PAGE 9
AD9430 TIMING DIAGRAMS CLK+ CLK– DS+ DS– tSDS tHDS PORT A DA11–DA0 STATIC PORT B DB11–DB0 STATIC tPD 14 CYCLES INTERLEAVED DATA OUT INVALID tV N N+2 INVALID INVALID N+1 N+3 PARALLEL DATA OUT PORT A DA11–DA0 STATIC INVALID INVALID N N+2 PORT B DB11–DB0 STATIC INVALID INVALID N+1 N+3 tCPD 02607-002 DCO– STATIC DCO+ Figure 2. CMOS Timing Diagram N–1 N N+1 AIN tEL tEH 1/fS CLK+ CLK– tPD N–14 DATA OUT N–13 N N+1 14 CYCLES 02607-003 DCO+ DCO– tCPD Figure 3.
PAGE 10
AD9430 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5.
PAGE 11
AD9430 DA5 DA6 DA7 DA8 DA9 DA10 DRGND DRVDD DA11 OR_A AGND AGND AVDD AVDD AVDD AGND AGND AGND AVDD AVDD AGND AGND AVDD AVDD AGND PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 DRVDD 74 DRGND 3 73 DA4 AGND 4 72 DA3 S2 5 71 DA2 S1 6 70 DA1 DNC 7 69 DA0 AVDD 8 68 DNC 67 DRGND 66 DNC 65 DNC 64 DCO+ AGND 13 63 DCO– AVDD 14 62 DRVDD AVDD 15 61 DRGND AGND 16 60 OR_B A
PAGE 12
AD9430 Pin Number 36 37 44 45 46 47, 54, 62, 75, 83 48, 53, 61, 67, 74, 82 49 50 51 52 55 56 57 58 59 60 63 64 69 70 71 72 73 76 77 78 79 80 81 84 85 1 2 Mnemonic CLK+ CLK– DB0 DB1 DB2 DRVDD DRGND1 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 OR_B DCO– DCO+ DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 OR_A Description Clock Input—True. Clock Input—Complement. B Port Output Data Bit (LSB). B Port Output Data Bit. B Port Output Data Bit. 3.3 V Digital Output Supply (3.0 V to 3.6 V). Digital Output Ground.
PAGE 13
D9– D9+ D10– D10+ D11– D11+ DRGND DRVDD OR– OR+ AGND AGND AVDD AVDD AVDD AGND AGND AGND AVDD AVDD AGND AGND AVDD AVDD AGND AD9430 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 DRVDD 74 DRGND 3 73 D8+ AGND 4 72 D8– S2 5 71 D7+ S1 6 70 D7– LVDSBIAS 7 69 D6+ AVDD 8 68 D6– 67 DRGND 66 D5+ 65 D5– 64 DCO+ AGND 13 63 DCO– AVDD 14 62 DRVDD AVDD 15 61 DRGND AGND 16 60 D4+ AGND 17 59 D4– AVDD 18 58 D3+ AVDD
PAGE 14
AD9430 Pin Number 22 32 36 37 47, 54, 62, 75, 83 48, 53, 61, 67, 74, 82 49 50 51 52 55 56 57 58 59 60 63 64 65 66 68 69 70 71 72 73 76 77 78 79 80 81 84 85 1 2 Mnemonic VIN– GND CLK+ CLK– DRVDD DRGND1 D0– D0+ D1– D1+ D2– D2+ D3– D3+ D4– D4+ DCO– DCO+ D5– D5+ D6– D6+ D7– D7+ D8– D8+ D9– D9+ D10– D10+ D11– D11+ OR– OR+ Description Analog Input—Complement. Data Sync (Input)—Not Used in LVDS Mode. Tie to GND. Clock Input—True (LVPECL Levels). Clock Input—Complement (LVPECL Levels). 3.
PAGE 15
AD9430 EQUIVALENT CIRCUITS FULL SCALE K AVDD S5 = 0 —> K = 1.24 S5 = 1 —> K = 0.62 12kΩ CLK+ OR DS+ 150Ω 0.1μF VREF 12kΩ – + CLK– OR DS– 150Ω A1 1V 200Ω 10kΩ SENSE 1kΩ DISABLE A1 VDD 02607-009 02607-080 10kΩ Figure 6. ENCODE and DS Input Figure 9. VREF, SENSE I/O AVDD DRVDD 3.5kΩ 3.5kΩ DX VIN– VIN+ 02607-007 20kΩ Figure 7. Analog Inputs 02607-010 20kΩ Figure 10. Data Outputs (CMOS Mode) DRVDD VDD S1, S2, S4, S5 V V DX– DX+ V V 02607-008 02607-011 30kΩ Figure 8.
PAGE 16
AD9430 TYPICAL PERFORMANCE CHARACTERISTICS Charts at 170 MSPS, 210 MSPS for –170, –210 grades, respectively. AVDD, DRVDD = 3.3 V, T = 25°C, AIN differential drive, full scale = 1.536 V, internal reference unless otherwise noted. 0 0 SNR = 65.2dB SINAD = 65.1dB H2 = –88.8dBc H3 = –88.1dBc SFDR = 87dBc –20 –30 –20 –30 dB –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –100 –100 10 20 30 40 MHz 50 60 70 80 85 02607-012 –90 0 Figure 12. FFT: fs = 170 MSPS, AIN = 10.3 MHz @ −0.
PAGE 17
AD9430 0 0 SNR = 63.5dB SINAD = 62.6dB H2 = –79dBc H3 = –76.1dBc SFDR = 75.2dBc –20 –30 –30 –40 –40 dB dB –20 –50 –50 –60 –60 –70 –70 –80 –80 –90 –100 15 30 45 60 75 90 105 MHz 02607-018 –90 –100 0 SNR = 63.3dB SINAD = 63.1dB H2 = –80.38dBc H3 = –81.8dBc SFDR = 80.8dBc –10 Figure 18. FFT: fs = 210 MSPS, AIN = 65 MHz @ –0.5 dBFS, LVDS Mode 0 15 30 45 60 75 90 105 MHz 02607-021 –10 Figure 21. FFT: fs = 213 MSP, AIN = 100 MHz @ –0.
PAGE 18
AD9430 70 0 68 66 –170 SNR –30 64 62 dB dB –210 SNR 60 –60 SFDR = 63dBc 58 –210 SINAD 56 –90 –170 SINAD 54 02607-024 52 0 50 100 150 200 250 AIN (MHz) 300 350 400 Figure 24. SNR and SINAD vs. AIN Frequency, fs = 170 MSPS/210 MSPS, AIN @ –0.5 dBFS, LVDS Mode –120 0 10 20 30 40 50 60 MHz 70 80 90 100 02607-027 50 Figure 27.
PAGE 19
AD9430 80 OUTPUT SUPPLY CURRENT LVDS MODE 200 40 150 100 20 OUTPUT SUPPLY CURRENT CMOS MODE 50 0 100 120 140 160 180 ENCODE (MSPS) 0 220 200 70 SINAD 55 50 20 60 250 50 OUTPUT SUPPLY CURRENT LVDS MODE 200 40 150 30 OUTPUT SUPPLY CURRENT CMOS MODE 100 20 50 10 0 100 0 120 140 160 180 200 220 60 70 80 1.2 RO = 13Ω TYP 1.0 VREFOUT (V) 300 70 50 1.4 IDRVDD (OUTPUT SUPPLY CURRENT) (mA) ANALOG SUPPLY CURRENT CMOS MODE 40 Figure 33. SNR, SINAD, and SFDR vs.
PAGE 20
AD9430 1.250 1.00 0.75 1.245 0.25 1.240 LSB VREF (V) 0.50 1.235 0 –0.25 –0.50 1.230 2.7 2.9 3.1 3.3 AVDD (V) 3.5 3.7 –1.00 02607-036 1.225 2.5 3.9 Figure 36. VREF Output Voltage vs. AVDD 0 500 1000 1500 2000 CODE 2500 3000 3500 4000 02607-039 –0.75 Figure 39. Typical INL Plot (AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS, LVDS) 95 1.00 THIRD 0.75 90 SECOND 0.50 85 SFDR 0.25 dB LSB 80 0 75 –0.25 70 –0.50 SNR 60 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 –1.
PAGE 21
AD9430 90 0 80 –20 70 SFDR dBc LVDS MODE FULL SCALE = 1.5 60 –40 dB dB 50 SFDR dBc CMOS MODE FULL SCALE = 1.5 40 19.2 –60 30 –80 20 80dB REFERENCE LINE 10 –70 –60 –50 –40 –30 –20 0 –10 19.2 38.4 47.6 MHz Figure 42. SFDR vs. AIN Input Level, AIN @ 10.3 MHz, 210 MSPS, LVDS/CMOS Modes 02607-045 –80 –100 02607-042 0 –90 Figure 45. W-CDMA Four Channels Centered at 38.4 MHz, fs = 153.6 MHz, LVDS Mode 90 90 80 80 SFDR SNR 70 70 SFDR dBc LVDS MODE FULL SCALE = 1.
PAGE 22
AD9430 4.5 900 1.4 800 1.3 TPDR (DATA RISING) 3.0 2.5 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 Figure 48. Propagation Delay vs. Temperature, CMOS Mode, 170 MSPS/210 MSPS 700 1.2 600 1.1 500 1.0 400 0.9 VOD 300 0.8 200 0.7 100 0.6 0 0 2 4 6 8 10 12 0.5 14 RSET (kΩ) Figure 49. LVDS Output Swing, Common-Mode Voltage vs. RSET, Placed at LVDSBIAS, 170 MSPS/210 MSPS Rev. E | Page 22 of 44 02607-049 VDIF (mV) TPDF (DATA FALLING) 3.5 02607-048 ns 4.
PAGE 23
AD9430 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Full-Scale Input Power Expressed in dBm.
PAGE 24
AD9430 Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc.
PAGE 25
AD9430 APPLICATION NOTES THEORY OF OPERATION The AD9430 architecture is optimized for high speed and ease of use. The analog inputs drive an integrated high bandwidth track-and-hold circuit that samples the signal prior to quantization by the 12-bit core. For ease of use, the part includes an on-board reference and input logic that accepts TTL, CMOS, or LVPECL levels. The digital output logic levels are user selectable as standard 3 V CMOS or LVDS (ANSI-644 compatible) via Pin S2.
PAGE 26
AD9430 ANALOG INPUT DS INPUTS (DS+, DS–) The analog input to the AD9430 is a differential buffer. For best dynamic performance, impedances at VIN+ and VIN– should match. The analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. SNR and SINAD performance degrades significantly if the analog input is driven with a singleended signal.
PAGE 27
AD9430 LVDS OUTPUTS CLOCK OUTPUTS (DCO+, DCO–) The input ENCODE is divided by two (in CMOS mode) and available off chip at DCO+ and DCO–. These clocks can facilitate latching off chip, providing a low skew clocking solution (see Figure 2). The on-chip clock buffers should not drive more than 5 pF of capacitance to limit switching transient effects on performance.
PAGE 28
AD9430 EVALUATION BOARD, CMOS MODE The AD9430 evaluation board offers an easy way to test the AD9430 in CMOS mode. It requires a clock source, an analog input signal, and a 3.3 V power supply. The clock source is buffered on the board to provide the clocks for the ADC, latches, and data ready signals. The digital outputs and output clocks are available at two 40-pin connectors, P3 and P23.
PAGE 29
AD9430 CMOS DATA OUTPUTS OPTIONAL AMPLIFIER The ADC CMOS digital outputs are latched on the board by four LVT574s; the latch outputs are available at the two 40-pin connectors at Pin 11 through Pin 33 on P23 (Channel A) and Pin 11 through Pin 33 on P3 (Channel B). The latch output clocks (data ready) are available at Pin 37 on P23 (Channel A) and Pin 37 on P3 (Channel B). The data-ready clocks can be inverted at the timing controls section if needed.
PAGE 30
AD9430 TROUBLESHOOTING • • • • The AD9430 evaluation board is provided as a design example for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose. Verify power at IC pins. Check that all jumpers are in the correct position for the desired mode of operation. Verify that VREF is at 1.23 V. Run the clock and analog inputs at low speeds (10 MSPS/ 1 MHz) and monitor latch and ADC for toggling. 3.
PAGE 31
AD9430 Table 11. CMOS PCB Evaluation Board Bill of Material No. 1 Quantity 47 Reference Designator C1, C3–C11, C15–C44, C47, C48, C58–C62 Device Capacitor Package 0402 Value 0.1 μF 2 3 4 1 1 29 Capacitor Capacitor Capacitor 0402 0402 0402 10 pF 20 pF 0.
PAGE 32
P4 P21 PTMICA04 Figure 59. Evaluation Board Schematic—CMOS 02607-060 OPTIN R16 50Ω GND GND GND C6 0.1μF C7 0.1μF GND E15 COUT E7 E20 5 4 INX 2 3 T1 ENCODE C33 0.1μF GND J5 GND R27 50Ω R45 25Ω C5 0.1μF 4 3 T4 5 6 R4 3.8KΩ R3 3.8KΩ GND R11 0Ω R9 0Ω 2 1 SEE NOTE 1 FOR SINGLE ENDED INPUT 6 C34 0.
PAGE 33
AD9430 VCC C64 + 10μF C16 0.1μF C17 0.1μF C19 0.1μF C21 0.1μF C20 0.1μF C23 0.1μF C22 0.1μF C25 0.1μF C24 0.1μF C27 0.1μF C26 0.1μF C29 0.1μF C28 0.1μF C31 0.1μF C32 0.1μF C38 0.1μF C35 0.1μF GND VCC C68 0.01μF C69 0.01μF C70 0.01μF C71 0.01μF C72 0.01μF C73 0.01μF C74 0.01μF C75 0.01μF C76 0.01μF C77 0.01μF C78 0.01μF C46 0.01μF C50 0.01μF C51 0.01μF C52 0.01μF C45 0.01μF C44 0.1μF C42 0.1μF C41 0.1μF C15 0.1μF C37 0.1μF C79 0.01μF C80 0.01μF C81 0.01μF C82 0.
PAGE 34
Figure 63. PCB Ground Layer Figure 62. PCB Top-Side Copper 02607-084 02607-082 Figure 61. PCB Top-Side Silkscreen 02607-083 02607-081 AD9430 Figure 64. PCB Split Power Plane Rev.
PAGE 35
02607-085 02607-086 AD9430 Figure 65. PCB Bottom-Side Copper Figure 66. PCB Bottom-Side Silkscreen Rev.
PAGE 36
AD9430 EVALUATION BOARD, LVDS MODE The AD9430 evaluation board offers an easy way to test the AD9430 in LVDS mode. (The board is also compatible with the AD9411.) It requires a clock source, an analog input signal, and a 3.3 V power supply. The clock source is buffered on the board to provide the clocks for the ADC, latches, and a data-ready signal. The digital outputs and output clocks are available at a 40-pin connector, P23.
PAGE 37
AD9430 Table 13. LVDS PCB Evaluation Board Bill of Material No. 1 Quantity 33 2 4 Reference Designator C1, C4–C11, C15–C17, C19–C32, C35, C36, C58–C62 C3, C18, C39, C40 C33, C34, C37, C38 Device Capacitors Package 0603 Value 0.1 μF Comment C3, C18, C39, C40 not placed Capacitor 0402 0.
PAGE 38
02607-068 GND NC NC R27 50Ω R17 510Ω C5 0.1μF C30 0.1μF AMPIN 14 15 16 17 18 19 20 VCC VCC GND GND VCC VCC GND R18 510Ω VDL 25 24 23 22 2 3 4 U3 VEE 5 Q QN GND C8 0.1μF D DN VBB GND GND R5 50Ω R19 150Ω ELOUTB ELOUT R20 150Ω 6 7 GND C36 0.1μF VCC 8 E45 E46 GND 10EL16 E47 C13 20pF GND VCC GND 13 GND 21 12 GND 11 10 9 7 6 5 4 3 GND R30 1kΩ 2 1 8 VCC R42 GND 25Ω C2 10pF C3 0.1μF GND C1 0.
PAGE 39
AD9430 VCC + C64 10μF C16 0.1μF C17 0.1μF C19 0.1μF C21 0.1μF C23 0.1μF C20 0.1μF C22 0.1μF C25 0.1μF C24 0.1μF C27 0.1μF C26 0.1μF C29 0.1μF C28 0.1μF C31 0.1μF C32 0.1μF C35 0.1μF GND DRVDD VDL + C65 10μF C61 0.1μF C62 0.1μF C60 0.1μF C59 0.1μF C58 0.1μF + C66 10μF VREF C18 0.
PAGE 40
AD9430 02607-073 02607-071 F Figure 72. PCB Ground Layer—LVDS 02607-074 02607-072 Figure 70. PCB Top-Side Silkscreen—LVDS Figure 71. PCB Top-Side Copper—LVDS Figure 73. PCB Split Power Plane—LVDS Rev.
PAGE 41
02607-075 02607-076 AD9430 Figure 74. PCB Bottom-Side Copper—LVDS Figure 75. PCB Bottom-Side Silkscreen—LVDS Rev.
PAGE 42
AD9430 OUTLINE DIMENSIONS 0.75 0.60 0.45 16.00 BSC SQ 1.20 MAX 14.00 BSC SQ 100 1 SEATING PLANE 76 76 75 100 1 75 PIN 1 BOTTOM VIEW (PINS UP) TOP VIEW (PINS DOWN) CONDUCTIVE HEAT SINK 51 50 25 50 1.05 1.00 0.95 7° 3.5° 0° 0.50 BSC 0.27 0.22 0.17 0.15 0.05 26 6.50 NOM COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD 021809-A 51 25 26 0.20 0.
PAGE 43
AD9430 NOTES Rev.