Datasheet

AD9410
Rev. A | Page 8 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
01679-003
PIN 1
IDENTIFIER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23 24
25 26
27
28 29 30 31
32
33
34 35
36 37 38 39 40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
6162636465666768697071727374757677787980
AD9410
TOP VIEW
80-LEAD THIN QUAD FLAT PACKAGE
(Not to Scale)
AGND
AGND
V
CC
REF
OUT
REF
IN
DNC
V
CC
AGND
AGND
A
IN
AGND
AGND
V
CC
V
CC
AGND
AGND
CLK+
AGND
V
DD
DGND
D
A4
D
A3
D
A2
D
A1
D
A0
(LSB)
V
DD
DGND
DCO
DCO
DGND
V
DD
OR
B
D
B9
(MSB)
D
B8
D
B7
D
B6
D
B5
V
DD
I/P DFS AGND AGND V
D
V
D
AGND AGND AGND AGND V
D
V
D
DGND V
DD
OR
A
D
A9
(MSB)
D
A8
D
A7
D
A6
D
A5
AGND
DS
AGND
V
D
V
D
AGND AGND AGND AGND
V
D
V
D
DGND
V
DD
(LSB) D
B0
D
B1
D
B2
D
B3
D
B4
DGND
A
IN
CLK–
DS
DNC = DO NOT CONNECT.
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Function
1, 2, 8, 9, 12, 13, 16,
17, 20, 21, 24, 27, 28,
29, 30, 71, 72, 73, 74,
77, 78
AGND Analog Ground.
3, 7, 14, 15 V
CC
5 V Supply. (Regulate to within ±5%.)
4 REF
OUT
Internal Reference Output.
5 REF
IN
Internal Reference Input.
6 DNC Do Not Connect.
10 A
IN
Analog Input—True.
11
A
IN
Analog Input—Complement.
18 CLK+ Clock Input—True.
19 CLK− Clock Input—Complement.
22 DS Data Sync (Input)—True. Tie low if not used.
23
DS
Data Sync (Input)—Complement. Float and decouple with 0.1 μF capacitor if not used.
25, 26, 31, 32, 69, 70,
75, 76
V
D
3.3 V Analog Supply. (Regulate to within ±5%.)
33, 40, 49, 52, 59, 68 DGND Digital Ground.
34, 41, 48, 53, 60, 67 V
DD
3.3 V Digital Output Supply. (2.5 V to 3.6 V)
35 to 39 D
B0
to D
B4
Digital Data Output for Channel B. (LSB = D
B0
.)
42 to 46 D
B5
to D
B9
Digital Data Output for Channel B. (MSB = D
B9
.)
47 OR
B
Data Overrange for Channel B.
50
DCO
Clock Output—Complement.