Datasheet

AD9410
Rev. A | Page 6 of 20
t
EH
t
EL
1/ f
S
t
A
t
SDS
t
CPD
SAMPLE N–2
SAMPLE N–1
SAMPLE N
SAMPLE N+1 SAMPLE N+2
SAMPLE N+3
SAMPLE N+4
SAMPLE N+5
SAMPLE N+6
t
V
t
PD
t
HDS
STATIC
STATIC
STATIC
STATIC
STATIC INVALIDINVALID INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
DATA N+1 DATA N+3
DATA N DATA N+2
DATA N+1
DATA N DATA N+2
INTERLEAVED DATA OUT
PARALLEL DATA OUT
A
IN
CLK+
DS
PORT A
D7 TO D0
PORT B
D7 TO D0
DCO
PORT A
D7 TO D0
PORT B
D7 TO D0
CLK–
DS
DCO
01679-002
Figure 2. Timing Diagram