Datasheet

AD9410
Rev. A | Page 4 of 20
SWITCHING SPECIFICATIONS
V
DD
= 3.3 V, V
D
= 3.3 V, V
CC
= 5.0 V; 2.5 V external reference; A
IN
= −0.5 dBFS; clock input = 210 MSPS; T
A
= 25°C; unless otherwise noted.
Table 2.
Parameter Temp Test Level Min Typ Max Unit
SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 210 MSPS
Minimum Conversion Rate Full IV 100 MSPS
Clock Pulse Width High, t
EH
25°C IV 1.2 2.4 ns
Clock Pulse Width Low, t
EL
25°C IV 1.2 2.4 ns
Aperture Delay, t
A
25°C V 1.0 ns
Aperture Uncertainty (Jitter) 25°C V 0.65 ps rms
Output Valid Time, t
V
Full VI 3.0 ns
Output Propagation Delay, t
PD
Full VI 7.4 ns
Output Rise Time, t
R
25°C V 1.8 ns
Output Fall Time, t
F
25°C V 1.4 ns
CLKOUT Propagation Delay, t
CPD
1
Full VI 2.6 4.8 6.4 ns
Data to DCO Skew, (t
PD
– t
CPD
) Full IV 0 1 2 ns
DS Setup Time, t
SDS
Full IV 0.5 ns
DS Hold Time, t
HDS
Full IV 0 ns
Interleaved Mode (A, B Latency) Full VI A = 6, B = 6 Cycles
Parallel Mode (A, B Latency) Full VI A = 7, B = 6 Cycles
1
C
LOAD
= 5 pF.
DIGITAL SPECIFICATIONS
V
DD
= 3.3 V, V
D
= 3.3 V, V
CC
= 5.0 V; 2.5 V external reference; A
IN
= −0.5 dBFS; clock input = 210 MSPS; T
A
= 25°C; unless otherwise noted.
Table 3.
Parameter Temp Test Level Min Typ Max Unit
DIGITAL INPUTS
DFS, Input Logic 1 Voltage Full IV 4 V
DFS, Input Logic 0 Voltage Full IV 1 V
DFS, Input Logic 1 Current Full V 50 μA
DFS, Input Logic 0 Current Full V 50 μA
I/P Input Logic 1 Current
1
Full V 400 μA
I/P Input Logic 0 Current
1
Full V 1 μA
CLK+, CLK− Differential Input Voltage Full IV 0.4 V
CLK+, CLK− Differential Input Resistance Full V 1.6 kΩ
CLK+, CLK− Common-Mode Input Voltage
2
Full V 1.5 V
DS, DS Differential Input Voltage
Full IV 0.4 V
DS, DS Common-Mode Input Voltage
Full V 1.5 V
Digital Input Pin Capacitance 25°C V 3 pF
DIGITAL OUTPUTS
Logic 1 Voltage (V
DD
= 3.3 V) Full VI V
DD
– 0.05 V
Logic 0 Voltage (V
DD
= 3.3 V) Full VI 0.05 V
Output Coding Binary or Twos Complement
1
I/P pin Logic 1 = 5 V, Logic 0 = GND. It is recommended to use a series 2.5 kΩ (±10%) resistor to V
DD
when setting to Logic 1 to limit input current.
2
See Clock Input section.