HDMI™ Display Interface AD9398 FEATURES Advanced TVs HDTVs Projectors LCD monitors SDA SERIAL REGISTER AND POWER MANAGEMENT YCbCr (4:2:2 OR 4:4:4) R/G/B 8 × 3 OR YCbCr Rx0+ Rx0– 2 DATACK Rx1+ HSYNC Rx1– Rx2+ HDMI RECEIVER Rx2– VSYNC DE 2 DATACK HSOUT VSOUT DE RxC+ S/PDIF OUT RxC– 8-CHANNEL I2S RTERM MCLK LRCLK MCL MDA HDCP DDCSCL DDCSDA AD9398 05678-001 APPLICATIONS R/G/B 8 × 3 SCL RGB ↔YCbCr COLORSPACE CONVERTER HDMI interface Supports high bandwidth digital content protection R
AD9398 TABLE OF CONTENTS Features .............................................................................................. 1 4:4:4 to 4:2:2 Filter ...................................................................... 11 Applications....................................................................................... 1 Audio PLL Setup......................................................................... 12 Functional Block Diagram ..............................................................
AD9398 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VDD, VD = 3.3 V, DVDD = PVDD = 1.8 V, ADC clock = maximum. Table 1.
AD9398 Parameter POWER SUPPLY VD Supply Voltage VDD Supply Voltage DVDD Supply Voltage PVDD Supply Voltage IVD Supply Current (Typical Pattern) 1 IVDD Supply Current (Typical Pattern) 2 IDVDD Supply Current (Typical Pattern)1, Test Level Conditions IV IV IV IV V V V AD9398KSTZ-100 Min Typ Max AD9398KSTZ-150 Min Typ Max 3.15 1.7 1.7 1.7 3.15 1.7 1.7 1.7 3.3 3.3 1.8 1.8 80 40 88 3.47 347 1.9 1.9 100 100 3 110 26 130 35 Unit 3.3 3.3 1.8 1.8 80 55 110 3.47 347 1.9 1.
AD9398 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VD VDD DVDD PVDD Analog Inputs Digital Inputs Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature Rating 3.6 V 3.6 V 1.98 V 1.98 V VD to 0.0 V 5 V to 0.0 V 20 mA −25°C to +85°C −65°C to +150°C 150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
AD9398 VDD RED 0 RED 1 RED 2 RED 3 RED 4 RED 5 RED 6 RED 7 GND VDD DATACK DE HSOUT NC VSOUT O/E FIELD SDA SCL PWRDN VD NC GND NC VD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 74 NC 3 73 NC GREEN 5 4 72 VD GREEN 4 5 71 NC GREEN 3 6 70 NC GREEN 2 7 69 GND GREEN 1 8 68 NC GREEN 0 9 67 VD VDD 10 AD9398 66 NC GND 11 65 GND BLUE 7 12 TOP VIEW
AD9398 Pin Type POWER SUPPLY Pin No.
AD9398 Mnemonic RTERM AUDIO DATA OUTPUT S/PDIF I2S0 to I2S3 MCLKIN MCLKOUT SCLK LRCLK SERIAL PORT SDA SCL DDCSDA DDCSCL MDA MCL DATA OUTPUTS RED [7:0] GREEN [7:0] BLUE [7:0] DATA CLOCK OUTPUT DATACK POWER SUPPLY 1 VD (3.3 V) VDD (1.8 V to 3.3 V) PVDD (1.8 V) DVDD (1.8 V) GND 1 Description RTERM is the termination resistor used to drive the AD9398 internally to a precise 50 Ω termination for TMDS lines. This should be a 500 Ω 1% tolerance resistor. Sony/Philips Digital Interface.
AD9398 DESIGN GUIDE GENERAL DESCRIPTION SERIAL CONTROL PORT The AD9398 is a fully integrated solution for receiving DVI/HDMI signals and is capable of decoding HDCPencrypted signals through connections to an external EEPROM. The circuit is ideal for providing an interface for HDTV monitors or as the front end to high performance video scan converters. The serial control port is designed for 3.3 V logic. However, it is tolerant of 5 V logic signals.
AD9398 SYNC SEPARATOR THRESHOLD TIMING The output data clock signal is created so that its rising edge always occurs between data transitions and can be used to latch the output data externally. FIELD 1 QUADRANT 2 FIELD 0 3 4 1 FIELD 1 2 FIELD 0 4 1 HSIN VSIN Figure 3 shows the timing operation of the AD9398. O/E FIELD tDCYCLE ODD FIELD DATACK 05678-005 VSOUT tPER Figure 5. VSYNC Filter—Odd HDMI RECEIVER tSKEW 05678-003 DATA HSOUT Figure 3.
AD9398 4:4:4 TO 4:2:2 FILTER The AD9398 contains a filter that allows it to convert a signal from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the maximum accuracy and fidelity of the original signal. Input Color Space to Output Color Space The AD9398 can accept a wide variety of input formats and either retain that format or convert to another. Input formats supported are: • 4:4:4 YCrCb 8-bit • 4:2:2 YCrCb 8-, 10-, and 12-bit • RGB 8-bit One of the three channels is represented in Figure 6.
AD9398 Data contained in the audio infoframes, among other registers, define for the AD9398 HDMI receiver not only the type of audio, but the sampling frequency (fS). The audio infoframe also contains information about the N and CTS values used to recreate the clock. With this information, it is possible to regenerate the audio sampling frequency. The audio clock is regenerated by dividing the 20-bit CTS value into the TMDS clock, then multiplying by the 20-bit N value.
AD9398 AUDIO BOARD LEVEL MUTING This information is the fundamental difference between DVI and HDMI transmissions and is located in read-only registers R0x5A to R0xEE. In addition to this information, registers are provided to indicate that new information has been received. Registers with addresses ending in 0xX7 or 0xXF beginning at R0x87 contain the new data flag (NDF) information. These registers contain the same information and all are reset once any of them are read.
AD9398 2-WIRE SERIAL REGISTER MAP The AD9398 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table 11.
AD9398 Hex Address 0x25 0x26 Read/Write or Read Only Read/Write Read/Write Bits [5] Default Value **1***** Register Name DE Output Polarity [4] ***1**** Field Output Polarity [0] *******0 Output CLK Invert [7:6] 01****** Output CLK Select [5:4] **11**** Output Drive Strength [3:2] ****00** Output Mode [1] [0] ******1* *******0 [7] [5] [4] [3] 0******* **0***** ***0**** ****1*** Primary Output Enable Secondary Output Enable Output Three-State SPDIF Three-State I2S Three-State Powe
AD9398 Hex Address Read/Write or Read Only Bits [4] Default Value ***0**** Register Name BT656 EN [3] [2:0] ****0*** *****000 Force DE Generation Interlace Offset 0x28 Read/Write [7:2] 011000** VS Delay 0x29 Read/Write [1:0] [7:0] ******01 00000100 HS Delay MSB HS Delay 0x2A 0x2B 0x2C 0x2D 0x2E Read/Write Read/Write Read/Write Read/Write Read/Write [3:0] [7:0] [3:0] [7:0] [7] ****0101 00000000 ****0010 11010000 0******* Line Width MSB Line Width Screen Height MSB Screen Height Ctrl EN
AD9398 Hex Address Read/Write or Read Only Bits [5] Default Value **0***** Register Name Low Freq Mode [4] ***0**** Low Freq Override [3] ****0*** Up Conversion Mode [2] [1] *****0** ******0* CrCb Filter Enable CSC_Enable 0x35 Read/Write [6:5] *01* **** CSC_Mode 0x36 Read/Write [4:0] [7:0] ***01100 01010010 CSC_Coeff_A1 MSB CSC_Coeff_A1 LSB 0x37 0x38 Read/Write Read/Write [4:0] [7:0] ***01000 00000000 CSC_Coeff_A2 MSB CSC_Coeff_A2 LSB 0x39 0x3A Read/Write Read/Write [4:0] [7:0
AD9398 Hex Address 0x44 Read/Write or Read Only Read/Write Bits [7:0] Default Value 10010010 Register Name CSC_Coeff_B4 LSB 0x45 0x46 Read/Write Read/Write [4:0] [7:0] ***00000 00000000 CSC_Coeff_C1 MSB CSC_Coeff_C1 LSB 0x47 0x48 Read/Write Read/Write [4:0] [7:0] ***01000 00000000 CSC_Coeff_C2 MSB CSC_Coeff_C2 LSB 0x49 0x4A Read/Write Read/Write [4:0] [7:0] ***01110 10000111 CSC_Coeff_C3 MSB CSC_Coeff_C3 LSB 0x4B 0x4C Read/Write Read/Write [4:0] [7:0] ***11000 10111101 CSC_Coeff_C4 M
AD9398 Hex Address Read/Write or Read Only 0x5B 0x5E Read Read Bits [3] [7:6] [5:3] Default Value Register Name HDMI Mode Channel Status 2 1 0 0x5F Read [7:0] 0x60 Read 0x61 Read [7:4] [3:0] [5:4] [3:0] 0x62 Read [3:0] 0x7B Read [7:0] 0x7C 0x7D Read Read Read [7:0] [7:4] [3:0] 0x7E Read [7:0] Description 4 ACP packets. 5 ISRC1 packets. 6 ISRC2 packets. 0 = DVI, 1 = HDMI. Mode = 00. All others are reserved.
AD9398 Hex Address 0x7F Read/Write or Read Only Read Bits [7:0] 0x80 0x81 Read Read [7:0] [6:5] 0x82 0x83 Read Read Default Value Register Name N [7:0] AVI Infoframe AVI Infoframe Version 4 Active Format Information Status [3:2] Bar Information [1:0] Scan Information [7:6] Colorimetry [5:4] Picture Aspect Ratio [3:0] Active Format Aspect Ratio [1:0] Nonuniform Picture Scaling 0x84 Read [6:0] 0x85 Read [3:0] Video Identification Code Pixel Repeat 0x86 Read [7:0] Active Lin
AD9398 Hex Address 0x87 Read/Write or Read Only Read Bits [6:0] 0x88 0x89 Read Read [7:0] [7:0] Active Line Start MSB Active Line End LSB 0x8A 0x8B Read Read [7:0] [7:0] Active Line End MSB Active Pixel Start LSB 0x8C 0x8D Read Read [7:0] [7:0] Active Pixel Start MSB Active Pixel End LSB 0x8E 0x8F 0x90 Read Read Read [7:0] [6:0] [7:0] 0x91 Read [7:4] Active Pixel End MSB New Data Flags Audio Infoframe Version Audio Coding Type [2:0] Audio Coding Count [4:2] Sampling Frequency 0x92
AD9398 Hex Address Read/Write or Read Only Bits [1:0] 0x93 Read [7:0] 0x94 Read [7:0] 7 0x95 Read [6:3] 0x96 0x97 Read Read [7:0] [6:0] 0x98 Read [7:0] 0x99 Read [7:0] 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 Read Read Read Read Read Read Read Read Read [7:0] [7:0] [7:0] [7:0] [7:0] [6:0] [7:0] [7:0] [7:0] 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE Read Read Read Read Read Read Read Read Read Read Read Read [7:0] [7:0] [7:0] [7:0] [7:0] [6:0] [7:0] [7:0] [7:0]
AD9398 Hex Address 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 Read/Write or Read Only Read Read Read Read Read Read Bits [6:0] [7:0] [7:0] [7:0] [7:0] [7:0] 0xB7 Read [6:0] 0xB8 Read [7:0] 0xB9 Read [7:0] 0xBA 0xBB 0xBC Read Read Read [7:0] [7:0] [7:0] 4 0xBD Read [1:0] 0xBE 0xBF 0xC0 Read Read Read [7:0] [6:0] [7:0] 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 Read Read Read Read Rea Read Read [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [6:0] Default Value Register Name New Data Flags PD13 PD14 PD15 PD16 Source
AD9398 Hex Address 0xC8 Read/Write or Read Only Read Bits 7 Default Value Register Name ISRC1 Continued 6 ISRC1 Valid [2:0] ISRC1 Status 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC Read Read Read Read Read Read Read Read Read Read Read Read Read Read Read Read Read Read Read Read [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [6:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [6:0] [7:0] [7:0] [7:0] [7:0] [7:0] ISRC1 Packet Byte 0 ISRC1_PB1 ISRC1_PB2 IS
AD9398 2-WIRE SERIAL CONTROL REGISTER DETAILS CHIP IDENTIFICATION 0x12—Bit[4] VSYNC Polarity Override 0x00—Bits[7:0] Chip Revision 0 = auto VSYNC polarity, 1 = manual VSYNC polarity. Manual VSYNC polarity is defined in Register 0x11, Bit 5. The powerup default is 0. An 8-bit value that reflects the current chip revision. 0x11—Bit[7] HSYNC Source 0x17—Bits[3:0] HSYNCs per VSYNC MSBs 0 = HSYNC, 1 = SOG. The power-up default is 0. These selections are ignored if Register 0x11, Bit 6 = 0.
AD9398 0x23—Bits[7:0] HSYNC Duration 0x25—Bits[5:4] Output Drive Strength An 8-bit register that sets the duration of the HSYNC output pulse. The leading edge of the HSYNC output is triggered by the internally generated, phase-adjusted PLL feedback clock. The AD9398 then counts a number of pixel clocks equal to the value in this register. This triggers the trailing edge of the HSYNC output, which is also phase-adjusted. The power-up default is 32.
AD9398 0x26—Bit[7] Output Three-State 0x27—Bit[5] MCLK External Enable When enabled, this bit puts all outputs (except SOGOUT) in a high impedance state. 0 = normal outputs. 1 = all outputs (except SOGOUT) in high impedance mode. The power-up default setting is 0. This bit enables the MCLK to be supplied externally. If an external MCLK is used, then it must be locked to the video clock according to the CTS and N available in the I2C.
AD9398 0x2E—Bit[7] Ctrl Enable 0x30—Bit[5] DVI HSYNC Polarity When set, this bit allows Ctrl [3:0] signals decoded from the DVI to be output on the I2S data pins. 0 = I2S signals on I2S lines. 1 = Ctrl[3:0] output on I2S lines. The power-up default setting is 0. This read-only bit indicates the polarity of the DVI HSYNC. 0 = DVI HSYNC polarity is low active. 1 = DVI HSYNC polarity is high active.
AD9398 0x33—Bit[7] Macrovision Detect Mode 0x35—Bits[6:5] Color Space Converter Mode 0 = standard definition. 1 = progressive scan mode. These two bits set the fixed-point position of the CSC coefficients, including the A4, B4, and C4 offsets. 0x33—Bit[6] Macrovision Settings Override This defines whether preset values are used for the MV line counts and pulse widths or the values stored in I2C registers. 0 = use hard-coded settings for line counts and pulse widths.
AD9398 0x40—Bits[7:0] CSC B2 LSBs 0x41—Bits[4:0] CSC B3 MSBs 0x58—Bits[2:0] MCLK fS_N These bits control the multiple of 128 fS used for MCLK out. The default value for the 13-bit B3 is 0x1E89. Table 19. MCLK fS_N [2:0] 0 1 2 3 4 5 6 7 0x42—Bits[7:0] CSC B3 LSBs 0x43—Bits[4:0] CSC B4 MSBs The default value for the 13-bit B4 is 0x0291. 0x44—Bits[7:0] CSC B4 LSBs 0x45—Bits[4:0] CSC C1 MSBs The default value for the 13-bit C1 is 0x0000.
AD9398 0x5E—Bits[7:6] Channel Status Mode 0x5E—Bits[5:3] PCM Audio Data 0x5E—Bit[2] Copyright Information 0x5E—Bit[1] Linear PCM Identification 0x5E—Bit[0] Use of Channel Status Block 0x5F—Bits[7:0] Channel Status Category Code 0x60—Bits[7:4] Channel Number 0x60—Bits[3:0] Source Number 0x61—Bits[5:4] Clock Accuracy 0x61—Bits[3:0] Sampling Frequency 0x81—Bits[1:0] Scan Information Table 24. S [1:0] 00 01 10 0x82—Bits[7:6] Colorimetry Table 25. C [1:0] 00 01 10 Table 21.
AD9398 0x87—Bit[6:0] New Data Flags (NDF) 0x91—Bits[7:4] Audio Coding Type This register indicates whether data in specific sections has changed. In the address space from 0x80 to 0xFF, each register address ending in 0b111 (for example, 0x87, 0x8F, 0x97, 0xAF) is an NDF register. They all have the same data and all are reset upon reading any one of them. Table 29. These bits identify the audio coding so that the receiver may process audio properly. Table 30.
AD9398 Table 33.
AD9398 0xA3—Bits[7:0] PD2 0xA4—Bits[7:0] PD3 0xA5—Bits[7:0] PD4 0xA6—Bits[7:0] PD5 0xA7—Bits[6:0] New Data Flags 0xBD—Bit[4] Field Repeat This defines whether the field is new or repeated. 0 = new field or picture. 1 = repeated field. 0xBD—Bits[1:0] MPEG Frame This identifies the frame as I, B, or P. See Register 0x87 for a description. Table 35.
AD9398 0xC9—Bits[7:0] ISRC1 Packet Byte 0 (ISRC1_PB0) 0xCA—Bits[7:0] ISRC1_PB1 0xCB—Bits[7:0] ISRC1_PB2 0xCC—Bits[7:0] ISRC1_PB3 0xCD—Bits[7:0] ISRC1_PB4 0xCE—Bits[7:0] ISRC1_PB5 0xCF—Bits[6:0] New Data Flags See Register 0x87 for a description. 0xD0—Bits[7:0] ISRC1_PB6 0xD1—Bits[7:0] ISRC1_PB7 0xD2—Bits[7:0] ISRC1_PB8 0xD3—Bits[7:0] ISRC1_PB9 0xD4—Bits[7:0] ISRC1_PB10 0xD5—Bits[7:0] ISRC1_PB11 0xD6—Bits[7:0] ISRC1_PB12 0xD7—Bits[6:0] New Data Flags See Register 0x87 for a description.
AD9398 2-WIRE SERIAL CONTROL PORT DATA TRANSFER VIA SERIAL INTERFACE A 2-wire serial interface control interface is provided in the AD9398. Up to two AD9398 devices can be connected to the 2-wire serial interface, with a unique address for each device. The 2-wire serial interface comprises a clock (SCL) and a bidirectional data (SDA) pin. The analog flat panel interface acts as a slave for receiving and transmitting data over the serial interface.
AD9398 SERIAL INTERFACE READ/WRITE EXAMPLES Write to one control register: Read from one control register: • Start signal • Start signal • Slave address byte (R/W bit = low) • Slave address byte (R/W bit = low) • Base address byte • Base address byte • Data byte to base address • Start signal • Stop signal • Slave address byte (R/W bit = high) Write to four consecutive control registers: • Data byte from base address • Start signal • Stop signal • Slave address byte (R/W bit =
AD9398 PCB LAYOUT RECOMMENDATIONS The AD9398 is a high precision, high speed digital device. To achieve the maximum performance from the part, it is important to have a well designed board. The following is a guide for designing a board using the AD9398. POWER SUPPLY BYPASSING It is recommended to bypass each power supply pin with a 0.1 μF capacitor. The exception is in the case where two or more supply pins are adjacent to each other.
AD9398 COLOR SPACE CONVERTER (CSC) COMMON SETTINGS Table 38.
AD9398 Table 42.
AD9398 OUTLINE DIMENSIONS 16.00 BSC SQ 1.60 MAX 0.75 0.60 0.45 100 1 76 75 PIN 1 14.00 BSC SQ TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY 25 51 50 26 VIEW A 0.50 BSC LEAD PITCH VIEW A ROTATED 90° CCW 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BED Figure 11.
AD9398 NOTES Rev.
AD9398 NOTES Rev.
AD9398 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05678-0-10/05(0) Rev.
