Datasheet

AD9393
Rev. 0 | Page 7 of 40
Pin No. Mnemonic Description Value
B8 VSOUT
VSYNC Output Clock (Phase-Aligned with DCLK). Vertical Sync Output. The
separated VSYNC from a composite signal or a direct passthrough of the
VSYNC signal. The polarity of this output can be controlled via the serial bus
bit (Register 0x24[6]).
V
DD
A9 O/E
Odd/Even Field Output for Interlaced Video. This output identifies whether the
current field (in an interlaced signal) is odd or even. The polarity of this signal
is programmable via Register 0x24[4].
V
DD
References
D10 FILT
Connection for External Filter Components for Audio PLL. For proper operation,
the audio clock generator PLL requires an external filter. Connect the filter
shown in Figure 6 to this pin. For optimal performance, minimize noise and
parasitics on this node. For more information, see the PCB Layout
Recommendations section.
PV
DD
Power Supply
1
E7, F7 V
D
HDMI Terminator Power Supply
(3.3 V). These pins supply power to the HDMI
terminators. They should be as quiet and filtered as possible.
3.3 V
D4, D5
V
DD
Digital Output Power Supply
(1.8 V to 3.3 V). A large number of output pins (up
to 27) switching at high speed (up to 80 MHz) generates many power supply
transients (noise). These supply pins are identified separately from the V
D
pins,
so output noise transferred into the sensitive circuitry can be minimized. If the
AD9393 is interfacing with lower voltage logic, V
DD
can be connected to a
lower supply voltage (as low as 1.8 V) for compatibility.
1.8 V to 3.3
V
F9, G9 PV
DD
PLL Power Supply (1.8 V). The most sensitive portion of the AD9393 is the
clock generation circuitry. These pins provide power to the clock PLL and help
the user design for optimal performance. The user should provide quiet,
noise-free power to these pins.
1.8 V
G6, G7 DV
DD
Digital Logic Power Supply (1.8 V). These pins supply power to the digital
logic.
1.8 V
C9, C10, D6, D7, D9, E4,
E9, E10,
F4, H10, J1, K3, K6, K9
GND
Ground. The ground return for all circuitry on chip. It is recommended that the
AD9393 be assembled on a single solid ground plane, with careful attention
to ground current paths.
0 V
Control
A10 SDA
Serial Port Data I/O for Programming the AD9393 Registers. The I
2
C address is
Address 0x98.
3.3 V CMOS
B10 SCL Serial Port Data Clock for Programming the AD9393 Registers. 3.3 V CMOS
HDCP
H9 DDC_SCL HDCP Slave Serial Port Data Clock for HDCP Communications to Transmitter. 3.3 V CMOS
J9 DDC_SDA
HDCP Slave Serial Port Data I/O for HDCP Communications to Transmitter. The
I
2
C address is Address 0x74 or Address 0x76.
3.3 V CMOS
F10 MDA Master Serial Port I/O to EEPROM with HDCP Keys—I
2
C Address is 0xA0. 3.3 V CMOS
G10 MCL Master Serial Port Data Clock to EEPROM with HDCP Keys. 3.3 V CMOS
Audio Data Outputs
J7 S/PDIF S/PDIF Digital Audio Output. V
DD
J6 I2S0 I
2
S Audio (Channel 1, Channel 2). Channel 0 and Channel 1 Audio Output. V
DD
J5 I2S1 I
2
S Audio (Channel 3, Channel 4). Channel 2 and Channel 3 Audio Output. V
DD
J4 I2S2 I
2
S Audio (Channel 5, Channel 6). Channel 4 and Channel 5 Audio Output. V
DD
J3 I2S3 I
2
S Audio (Channel 7, Channel 8). Channel 6 and Channel 7 Audio Output. V
DD
J2 MCLK Audio Master Clock Output for S/PDIF Data. V
DD
G4 SCLK Audio Serial Clock Output for I
2
S Data. V
DD
G5 LRCLK Data Output Clock for Left and Right Audio Channels. V
DD
Data Enable
B7 DE Data Enable for Active Data Pixels. 3.3 V CMOS
RTERM
J8 RTERM
Sets Internal Termination Resistance. Place a 500 Ω (1% tolerance) resistor from
this pin to ground. This sets the internal termination of TMDS lines to 50 Ω.
500 Ω
1
The supplies should be sequenced such that V
D
and V
DD
are never less than 300 mV below DV
DD
. At no time should DV
DD
be more than 300 mV greater than V
D
or V
DD
.