Datasheet

AD9393
Rev. 0 | Page 4 of 40
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS
V
DD
= V
D
=3.3 V, DV
DD
= PV
DD
= 1.8 V, unless otherwise noted.
Table 2.
Parameter
Test
Level
Conditions Min Typ Max Unit
DC DIGITAL I/O Specifications
High-Level Input Voltage (V
IH
) VI 2.5 V
Low-Level Input Voltage (V
IL
) VI 0.8 V
High-Level Output Voltage (V
OH
) VI V
DD
− 0.1 V
Low-Level Output Voltage (V
OL
) VI V
DD
− 0.1 0.1 V
DC SPECIFICATIONS
Output High Level IV Output drive = high strength 36 mA
I
OHD
(V
OUT
= V
OH
) IV Output drive = low strength 24 mA
Output Low Level IV Output drive = high strength 12 mA
I
OLD
(V
OUT
= V
OL
) IV Output drive = low strength 8 mA
DCLK High Level IV Output drive = high strength 40 mA
V
OHC
(V
OUT
= V
OH
) IV Output drive = low strength 20 mA
DCLK Low Level IV Output drive = high strength 30 mA
V
OLC
(V
OUT
= V
OL
) IV Output drive = low 15 mA
Differential Input Voltage, Single-Ended Amplitude IV 75 700 mV
POWER SUPPLY
V
D
IV 3.15 3.3 3.47 V
V
DD
IV 1.7 3.3 347 V
DV
DD
IV 1.7 1.8 1.9 V
PV
DD
IV 1.7 1.8 1.9 V
Power—54 MHz, YCrCb 422, CSC Disabled 485 mW
Supply Current (Worst Pattern)
1
I
VD
V 95 mA
I
VDD
V 18 mA
I
DVDD
2
V 51 mA
I
PVDD
V 26 mA
Power—74.25 MHz, RGB, CSC Disabled 593 mW
Supply Current (Worst Pattern)
1
I
VD
V 109 mA
I
VDD
V 38 mA
I
DVDD
V 66 mA
I
PVDD
V 26 mA
Power-Down Power VI 130 mW
AC SPECIFICATIONS
Intrapair (+ to −) Differential Input Skew (t
DPS
) IV 0.4 t
BIT
Channel-to-Channel Differential Input Skew (t
CCS
) IV 0.6 t
PIXEL
Low-to-High Transition Time for Data and Controls (D
LHT
) IV Output drive = high; C
L
= 10 pF 1000 ps
IV Output drive = low; C
L
= 5 pF ps
Low-to-High Transition Time for DCLK (D
LHT
) IV Output drive = high; C
L
= 10 pF 1000 ps
IV Output drive = low; C
L
= 5 pF ps
High-to-Low Transition Time for Data and Controls (D
HLT
) IV Output drive = high; C
L
= 10 pF 1000 ps
IV Output drive = low; C
L
= 5 pF ps
High-to-Low Transition Time for DCLK (D
HLT
) IV Output drive = high; C
L
= 10 pF 1000 ps
IV Output drive = low; C
L
= 5 pF ps
Clock-to-Data Skew
3
(t
SKEW
) IV −0.5 +2.0 ns
Duty Cycle, DCLK
3
IV 45 50 %
DCLK Frequency (f
CIP
) VI 20 80 MHz
1
Worst-case pattern is alternating black and white pixels.
2
DCLK load = 10 pF, data load = 5 pF.
3
Drive strength = high.