Datasheet
AD9393
Rev. 0 | Page 13 of 40
Hex Address Read/Write Bits
Default
Value Register Name Description
0x26 Read/write [7] 0xxxxxxx Output three-state Three-state the outputs.
[5] xx0xxxxx S/PDIF three-state Three-state the S/PDIF output.
[4] xxx0xxxx I
2
S three-state Three-state the I
2
S output and the MCLK output.
[3] xxxx1xxx Power-down ball polarity Sets polarity of power-down ball.
0 = active low.
1 = active high.
[2:1] xxxxx00x Power-down ball function Selects the function of the power-down ball.
0x = power-down.
1x = three-state outputs.
[0] xxxxxxx0 Power-down 0 = normal.
1 = power-down.
0x27 Read/write [7] 1xxxxxxx Auto power-down enable 0 = disable auto low power state.
1 = enable auto low power state.
[6] x0xxxxxx HDCP A0 Sets the LSB of the address of the HDCP I2C. Set to 1 only
for a second receiver in a dual-link configuration.
[5] xx0xxxxx Clock test Must be written to 0.
[4] xxx0xxxx BT656 EN Enables EAV/SAV codes to be inserted into the video
output data.
[3] xxxx0xxx Force DE generation Allows use of the internal DE generator—not the DE
transmitted over TMDS.
[2:0] xxxxx000 Interlace offset Sets the difference (in HSYNCs) in field length between
Field 0 and Field 1.
0x28 Read/write [7:2] 011000xx VSYNC delay Sets the delay (in lines) from the VSYNC leading edge to
the start of active video.
[1:0] xxxxxx01 HSYNC delay MSB HSYNC delay MSB of Register 0x29.
0x29 Read/write [7:0] 00000100 HSYNC delay LSB Sets the delay (in pixels) from the HSYNC leading edge to
the start of active video.
0x2A Read/write [3:0] xxxx0101 Line width MSB Line width MSB of Register 0x2B.
0x2B Read/write [7:0] 00000000 Line width LSB Sets the width of the active video line in pixels.
0x2C Read/write [3:0] xxxx0010 Screen height MSB Screen height MSB of Register 0x2D.
0x2D Read/write [7:0] 11010000 Screen height LSB Sets the height of the active screen in lines.
0x2E Read/write [7] 0xxxxxxx CTRL EN Allows CTRL[3:0] to be output on the I
2
S data pins.
[6:5] x00xxxxx I
2
S output mode 00 = I
2
S mode.
01 = right-justified.
10 = left-justified.
11 = raw IEC60958 mode.
[4:0] xxx11000 I
2
S bit width Sets the desired bit width for right-justified mode.
0x2F Read [6] x0xxxxxx TMDS sync detect Detects a TMDS DE.
[5] xx0xxxxx TMDS active Detects a TMDS clock.
[4] xxx0xxxx AV mute Gives the status of AV mute based on general control
packets.
[3] xxxx0xxx HDCP keys read Returns 1 when read of EEPROM keys is successful.
[2:0] xxxxx000 HDMI quality Returns quality number based on DE edges.
0x30 Read [6] x0xxxxxx HDMI content encrypted This bit is high when HDCP decryption is in use (content is
protected). The signal goes low when HDCP is not being
used. Use this bit to allow copying of the content. The bit
should be sampled at regular intervals because it can
change on a frame-by-frame basis.
[5] xx0xxxxx HDMI HSYNC polarity Returns HDMI HSYNC polarity.
[4] xxx0xxxx HDMI VSYNC polarity Returns HDMI VSYNC polarity.
[3:0] xxxx0000 HDMI pixel repetition Returns current HDMI pixel repetition amount. 0 = 1×,
1 = 2× … The clock and data outputs are automatically
decimated by this value.