Low Power HDMI Display Interface AD9393 APPLICATIONS Portable low power TV HDTV Projectors LCD monitor FUNCTIONAL BLOCK DIAGRAM SCL SDA SERIAL REGISTER AND POWER MANAGEMENT R/G/B 8 × 3 OR YCrCb DATACK Rx0+ HSYNC Rx0– Rx1+ Rx1– Rx2+ Rx2– RxC+ RxC– RTERM VSYNC DE HDMI RECEIVER D[23:0] DCLK HSOUT VSOUT DE SPDIF 8-CHANNEL I2S MCLK SCLK LRCLK MCL MDA DDC_SCL DDC_SDA HDCP AD9393 08043-001 HDMI interface Supports high bandwidth digital content protection RGB to YCrCb 2-way color conversion 1.8 V/3.
AD9393 TABLE OF CONTENTS Features .............................................................................................. 1 2-Wire Serial Register Map ........................................................... 12 Applications ....................................................................................... 1 2-Wire Serial Control Register Details ........................................ 22 Functional Block Diagram ..............................................................
AD9393 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VDD, VD = 3.3 V, DVDD = PVDD = 1.8 V, unless otherwise noted. Table 1.
AD9393 DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS VDD = VD =3.3 V, DVDD = PVDD = 1.8 V, unless otherwise noted. Table 2.
AD9393 ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS Table 3. Parameter VD VDD DVDD PVDD Digital Inputs Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature Rating 3.6 V 3.6 V 1.98 V 1.98 V 5 V to 0.0 V 20 mA −25°C to +85°C −65°C to +150°C 150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
AD9393 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 A D14 D15 D16 D18 D20 D22 DCLK HSOUT O/E SDA B D13 D12 D17 D19 D21 D23 DE VSOUT PD SCL C D11 D10 GND GND D D9 D8 VDD GND GND FILT E D7 D6 GND VD GND GND VD PVDD MDA DVDD PVDD MCL DDC_ SCL GND VDD GND AD9393 F D5 D4 GND G D3 D2 SCLK H D1 D0 J GND MCLK I2S3 I2S2 I2S1 I2S0 SPDIF RTERM DDC_ SDA Rx2+ K RxC– RxC+ GND Rx0– Rx0+ GND Rx1– Rx1+ GND Rx2–
AD9393 Pin No. B8 A9 Mnemonic VSOUT O/E Description VSYNC Output Clock (Phase-Aligned with DCLK). Vertical Sync Output. The separated VSYNC from a composite signal or a direct passthrough of the VSYNC signal. The polarity of this output can be controlled via the serial bus bit (Register 0x24[6]). Odd/Even Field Output for Interlaced Video. This output identifies whether the current field (in an interlaced signal) is odd or even. The polarity of this signal is programmable via Register 0x24[4].
AD9393 DESIGN GUIDE GENERAL DESCRIPTION SERIAL CONTROL PORT The AD9393 is a fully integrated solution for receiving DVI/ HDMI signals and is capable of decoding HDCP-encrypted signals through connections to an external EEPROM. The circuit is ideal for providing an interface for HDTV monitors or as the front end to high performance video scan converters. The serial control port is designed for 3.3 V logic. However, it is tolerant of 5 V logic signals.
AD9393 TIMING DE GENERATOR The output data clock signal is created so that its rising edge always occurs between data transitions and can be used to latch the output data externally. The AD9393 has an on-board generator for DE, for the start of active video (SAV), and for the end of active video (EAV), all of which are necessary for describing the complete data stream for a BT656-compatible output. This signal alerts the following circuitry, which are displayable video pixels.
AD9393 One of the three input channels is represented in Figure 4. In each processing channel, the three inputs are multiplied by three separate coefficients marked a1, a2, and a3. These coefficients are divided by 4096 to obtain nominal values ranging from −0.9998 to +0.9998. The variable labeled a4 is used as an offset control. The CSC_MODE setting is the same for all three processing channels. This multiplies all coefficients and offsets by a factor of 2CSC_MODE.
AD9393 This information is the fundamental difference between DVI and HDMI transmissions and is located in the read-only registers Register 0x5A to Register 0xEE. In addition to this information, registers are provided to indicate that new information has been received. Registers with addresses ending in 7 or F beginning with Register 0x87 contain the new data flags (NDF) information. All of these registers contain the same information and all are reset when any of them are read.
AD9393 2-WIRE SERIAL REGISTER MAP The AD9393 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table 9.
AD9393 Hex Address 0x26 0x27 Read/Write Read/write Read/write Bits [7] [5] [4] [3] Default Value 0xxxxxxx xx0xxxxx xxx0xxxx xxxx1xxx Register Name Output three-state S/PDIF three-state I2S three-state Power-down ball polarity [2:1] xxxxx00x Power-down ball function [0] xxxxxxx0 Power-down [7] 1xxxxxxx Auto power-down enable [6] x0xxxxxx HDCP A0 [5] [4] xx0xxxxx xxx0xxxx Clock test BT656 EN [3] xxxx0xxx Force DE generation [2:0] xxxxx000 Interlace offset 0x28 Read/write [7:2] 0
AD9393 Hex Address 0x34 Read/Write Read/write Bits [5:4] [3] Default Value xx00xxxx xxxx0xxx Register Name Audio setup Upconversion mode [2] [1] xxxxx0xx xxxxxx0x CrCb filter enable CSC_ENABLE 0x35 Read/write [6:5] x01xxxxx CSC_MODE 0x36 Read/write [4:0] [7:0] xxx01100 01010010 CSC_COEFF_A1 MSB CSC_COEFF_A1 LSB 0x37 0x38 Read/write Read/write [4:0] [7:0] xxx01000 00000000 CSC_COEFF_A2 MSB CSC_COEFF_A2 LSB 0x39 0x3A Read/write Read/write [4:0] [7:0] xxx00000 00000000 CSC_COEFF_A3 M
AD9393 Hex Address 0x47 0x48 Read/Write Read/write Read/write Bits [4:0] [7:0] Default Value xxx01000 00000000 Register Name CSC_COEFF_C2 MSB CSC_COEFF_C2 LSB 0x49 0x4A Read/write Read/write [4:0] [7:0] xxx01110 10000111 CSC_COEFF_C3 MSB CSC_COEFF_C3 LSB 0x4B 0x4C Read/write Read/write [4:0] [7:0] xxx11000 10111101 CSC_COEFF_C4 MSB CSC_COEFF_C4 LSB 0x4D 0x4E 0x4F 0x50 0x56 0x57 Read/write Read/write Read/write Read/write Read/write Read/write 0x58 Read/write [7:0] [7:0] [7:0] [7:0] [7:0]
AD9393 Hex Address 0x5E Read/Write Read Audio Channel Status 0x5F Read 0x60 Read 0x61 Read Bits [7:6] [5:3] Default Value 0 0 Register Name Channel status PCM audio data [2] 0 Copyright information [1] 0 Linear PCM identification [0] 0 Use of channel status block [7:0] 0 [7:4] [3:0] [5:4] 0 0 0 Channel status category code Channel number Source number Clock accuracy [3:0] 0 Sampling frequency 0x62 Read [3:0] 0 Word length 0x7B Read [7:0] 0 CTS[19:12] 0x7C 0x7D Read Read
AD9393 Hex Address 0x81 0x82 Read/Write Read Read Bits [6:5] Default Value 0 [4] 0 Active format information status [3:2] 0 Bar information [1:0] 0 Scan information [7:6] 0 Colorimetry [5:4] 0 Picture aspect ratio [3:0] 0 Active format aspect ratio Register Name Y[1:0] 0x83 Read [1:0] 0 Nonuniform picture scaling 0x84 Read [6:0] 0 Video identification code 0x85 Read [3:0] 0 Pixel repeat 0x86 Read [7:0] 0 Active line start LSB 0x87 Read [6:0] 0 New data flags
AD9393 Hex Address 0x88 0x89 Read/Write Read Read Bits [7:0] [7:0] Default Value 0 0 Register Name Active line start MSB Active line end LSB 0x8A 0x8B Read Read [7:0] [7:0] 0 0 Active line end MSB Active pixel start LSB 0x8C 0x8D Read Read [7:0] [7:0] 0 0 Active pixel start MSB Active pixel end LSB 0x8E 0x8F 0x90 0x91 Read Read Read Read [7:0] [6:0] [7:0] [7:4] 0 0 0 0 Active pixel end MSB New data flags Audio infoframe version Audio coding type [2:0] 0 Audio coding count [4:2] 0 Sa
AD9393 Hex Address Read/Write Bits 0x96 Read [7:0] 0x97 Read [6:0] Source Product Description (SPD) Infoframe 0x98 Read [7:0] Default Value 0 0 0 Register Name New data flags Source product description (SPD) infoframe version Vender Name Character 1 0x99 Read [7:0] 0 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 Read Read Read Read Read Read Read Read Read [7:0] [7:0] [7:0] [7:0] [7:0] [6:0] [7:0] [7:0] [7:0] 0 0 0 0 0 0 0 0 0 VN2 VN3 VN4 VN5 VN6 New data flags VN7 VN8 Product Description Characte
AD9393 Hex Address 0xBD Read/Write Read Bits [4] Default Value 0 Register Name Field repeat [1:0] 0 MPEG frame 0xBE 0xBF 0xC0 Read Read Read [7:0] [6:0] [7:0] 0 0 0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 Read Read Read Read Read Read Read Read [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [6:0] [7] 0 0 0 0 0 0 0 0 ACP Packet Byte 0 ACP_PB1 ACP_PB2 ACP_PB3 ACP_PB4 ACP_PB5 New data flags ISRC1 continued [6] 0 ISRC1 valid [2:0] 0 ISRC1 status New data flags Audio content protection packet (ACP) t
AD9393 Hex Address 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE Read/Write Read Read Read Read Read Read Read Read Read Read Read Read Bits [7:0] [7:0] [7:0] [7:0] [6:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Default Value 0 0 0 0 0 0 0 0 0 0 0 0 Register Name ISRC2_PB6 ISRC2_PB7 ISRC2_PB8 ISRC2_PB9 New data flags ISRC2_PB10 ISRC2_PB11 ISRC2_PB12 ISRC2_PB13 ISRC2_PB14 ISRC2_PB15 ISRC2_PB16 Rev. 0 | Page 21 of 40 Description ISRC2_PB6. ISRC2_PB7. ISRC2_PB8. ISRC2_PB9.
AD9393 2-WIRE SERIAL CONTROL REGISTER DETAILS This section describes certain register details. Note that not all registers are discussed in this section. CHIP IDENTIFICATION 0x00—Bits[7:0], Chip Revision An 8-bit value that reflects the current chip revision. 0x25—Bits[7:6], Output CLK Select These bits select the clock output on the DCLK ball. They include ½× clock, a 2× clock, a 90° phase shifted clock, or the normal pixel clock. The power-up default setting is 01. See Table 10.
AD9393 0x25—Bit[1], Primary Output Enable 0x26—Bit[0], Power-Down This bit places the primary output in active or high impedance mode. The primary output is designated when using either 4:2:2 or DDR 4:4:4. In these modes, the data on the red and green output channels (D[23:8]) is the primary output, whereas the output data on the blue channel (D[7:0], DDR YCrCb) is the secondary output. Double data rate 0 = primary output is in high impedance mode. 1 = primary output is enabled.
AD9393 BT656 GENERATION 0x2E—Bits[6:5], I2S Output Mode 0x27—Bit[4], BT656 EN These bits select between four options for the I2S output: I2S, right-justified, left-justified, or raw IEC60958 mode. The power-up default setting is 00. See Table 13. This bit enables the output to be BT656-compatible with the defined start of active video (SAV) and the end of active video (EAV) controls to be inserted.
AD9393 0x30—Bit[5], HDMI HSYNC Polarity COLOR SPACE CONVERSION This read-only bit indicates the polarity of the HDMI HSYNC. 0 = HDMI HSYNC polarity is active low. 1 = HDMI HSYNC polarity is active high. The default power up values for the color space converter coefficients (Register 0x34 through Register 0x4C) are set for ATSC RGB-to-YCrCb conversion. They are completely programmable for other conversions. 0x30—Bit[4], HDMI VSYNC Polarity This read-only bit indicates the polarity of the HDMI VSYNC.
AD9393 0x39—Bits[4:0], CSC_COEFF_A3 MSB and 0x3A— Bits[7:0], CSC_COEFF_A3 LSB 0x58—Bit[3], N_CTS_Disable This bit prevents the N/CTS packet on the link from writing to the N and CTS registers. The default value for the 13-bit A3 is 0x00000. 0x3B—Bits[4:0], CSC_COEFF_A4 MSB and 0x3C— Bits[7:0], CSC_COEFF_A4 LSB 0x58—Bits[2:0], MCLK FS_N The default value for the 13-bit A4 is 0x19D7. These bits control the multiple of 128 fS used for MCLK out. See Table 17.
AD9393 0x89—Bits[7:0], Active Line End LSB and 0x8A— Bits[7:0], Active Line End MSB 0x5B—Bit[3], HDMI Mode 0 = DVI, 1 = HDMI. 0x7B—Bits[7:0], CTS[19:12], 0x7C—Bits[7:0] CTS[11:4], and 0x7D—Bits[7:4], CTS[3:0] These bits are the most significant eight bits of a 20-bit word used with the 20-bit N term in the regeneration of the audio clock.
AD9393 0x93—Bits[7:0], Maximum Bit Rate Table 23. For compressed audio only, when this value is multiplied by 8 kHz, it represents the maximum bit rate. A value of 0x08 in this field yields a maximum bit rate of (8 kHz × 8 kHz = 64 kHz). Abbreviation FL FC FR FCL FCR RL RC RR RCL RCR LFE 0x94—Bits[7:0], Speaker Mapping Bits[4:0] define the suggested placement of speakers. Bits[7:5] are currently not available. See Table 23 and Table 24.
AD9393 0x95—Bits[6:3], Level Shift 0xB7—Bits[6:0], New Data Flags These bits define the amount of attenuation. The value directly corresponds to the amount of attenuation: for example, 0000 = 0 dB, 0001 = 1 dB, … ,1111 = 15 dB attenuation. See the 0x87—Bits[6:0], New Data Flags (NDF) section for a description. 0x97—Bits[6:0], New Data Flags These are the lower eight bits of 32 bits that specify the MPEG bit rate in hertz. See the 0x87—Bits[6:0], New Data Flags (NDF) section for a description.
AD9393 0xC8—Bit[6], ISRC1 Valid 0xD7—Bits[6:0], New Data Flags This bit is an indication of whether the ISRC1 packet bytes are valid. 0 = ISRC1 status bits and PBs not valid. 1 = ISRC1 status bits and PBs valid. See the 0x87—Bits[6:0], New Data Flags (NDF) section for a description. 0xC8—[2:0], ISRC Status This is transmitted only when the ISRC continued bit (Register 0xC8 Bit 7) is set to 1. These bits define where in the ISRC track the samples are.
AD9393 2-WIRE SERIAL CONTROL PORT A 2-wire serial interface control interface is provided in the AD9393. DATA TRANSFER VIA SERIAL INTERFACE The 2-wire serial interface is comprised of a clock (SCL) and a bidirectional data (SDA) ball. The HDMI flat panel interface acts as a slave for receiving and transmitting data over the serial interface. When the serial interface is not active, the logic levels on SCL and SDA are pulled high by external pull-up resistors.
AD9393 SERIAL INTERFACE READ/WRITE EXAMPLES Read from one control register: Write to one control register: 1. 2. 3. 4. 5. 1. 2. 3. 4. 5. 6. 7.
AD9393 PCB LAYOUT RECOMMENDATIONS The AD9393 is a high precision, high speed digital device. To achieve the maximum performance from the part, it is important to have a well laid-out board. The following sections are a guide for designing a board using the AD9393. POWER SUPPLY BYPASSING It is recommended to bypass each power supply ball with a 0.1 μF capacitor. The exception is in the case where two or more supply pins are adjacent to each other.
AD9393 COLOR SPACE CONVERTER (CSC) COMMON SETTINGS HDTV YCRCB (0 TO 255) TO RGB (0 TO 255) (DEFAULT SETTING FOR AD9393) Table 29.
AD9393 SDTV YCRCB (16 TO 235) TO RGB (0 TO 255) Table 38. Register Address Value 0x35 0x46 Red/Cr Coeff 1 0x36 0x63 0x37 0x04 Red/Cr Coeff 2 0x38 0xA8 0x39 0x00 Red/Cr Coeff 3 0x3A 0x00 0x3B 0x1C Red/Cr Offset 0x3C 0x84 Table 39. Register Address Value Green/Y Coeff 1 0x3D 0x3E 0x1C 0xC0 Green/Y Coeff 2 0x3F 0x40 0x04 0xA8 Green/Y Coeff 3 0x41 0x42 0x1E 0x6F Green/Y Offset 0x43 0x44 0x02 0x1E Table 40.
AD9393 RGB (0 TO 255) TO SDTV YCRCB (0 TO 255) Table 47. Register Address Value 0x35 0x08 Red/Cr Coeff 1 0x36 0x2D 0x37 0x19 Red/Cr Coeff 2 0x38 0x27 0x39 0x1E Red/Cr Coeff 3 0x3A 0xAC 0x3B 0x08 Red/Cr Offset 0x3C 0x00 Table 48. Register Address Value Green/Y Coeff 1 0x3D 0x3E 0x04 0xC9 Green/Y Coeff 2 0x3F 0x40 0x09 0x64 Green/Y Coeff 3 0x41 0x42 0x01 0xD3 Green/Y Offset 0x43 0x44 0x00 0x00 Table 49.
AD9393 OUTLINE DIMENSIONS A1 CORNER INDEX AREA 6.10 6.00 SQ 5.90 10 9 8 7 6 5 4 3 2 1 A B BALL A1 PAD CORNER TOP VIEW C 4.50 BSC SQ D E 0.50 BSC F G H J K BOTTOM VIEW 0.75 REF DETAIL A *1.40 MAX DETAIL A 0.65 MIN 0.15 MIN *COMPLIANT TO JEDEC STANDARDS MO-225 WITH THE EXCEPTION TO PACKAGE HEIGHT. COPLANARITY 0.08 MAX 010807-A 0.35 SEATING 0.30 PLANE 0.25 BALL DIAMETER Figure 9. 76-Pin Chip Scale Package Pin Grid Array [CSP_BGA] 6 mm × 6 mm × 1.
AD9393 NOTES Rev.
AD9393 NOTES Rev.
AD9393 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08043-0-10/09(0) Rev.
