Datasheet

Data Sheet AD9284
Rev. A | Page 9 of 24
Pin No. Mnemonic Type Description
16 D3+ Output Channel A/Channel B LVDS Output Data 3—True.
15 D3− Output Channel A/Channel B LVDS Output Data 3—Complement.
14 D2+ Output Channel A/Channel B LVDS Output Data 2—True.
13 D2− Output Channel A/Channel B LVDS Output Data 2—Complement.
12
D1+
Output
Channel A/Channel B LVDS Output Data 1—True.
11 D1− Output Channel A/Channel B LVDS Output Data 1—Complement.
10 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True.
9 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement.
18 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True.
17 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement.
SPI Control Pins
30 SCLK Input SPI Serial Clock.
31 SDIO/PWDN Input/output SPI Serial Data I/O (SDIO)/Power-Down Input in External Mode (PWDN).
32 CSB Input SPI Chip Select (Active Low).
Do Not Connect
3, 4, 6 DNC N/A Do Not Connect. Do not connect to this pin.