Datasheet

AD9284 Data Sheet
Rev. A | Page 6 of 24
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, −1.0 dBFS dierential input, 1.0 V internal reference, unless otherwise noted.
Table 4.
Parameter Temperature Min Typ Max Unit
CLOCK INPUT PARAMETERS
Input Clock Rate Full 30 250 MHz
CLK Period (t
CLK
) Full 4 ns
CLK Pulse Width High (t
CH
) Full 2 ns
DATA OUTPUT PARAMETERS
Data Propagation Delay (t
PD
) 3.7 ns
DCO Propagation Delay (t
DCO
) Full 3.7 ns
DCO to Data Skew (t
SKEW
) Full −280 −60 +100 ps
Pipeline Delay (Latency) Full 10.5 Cycles
Aperture Delay (t
A
) Full 1.0 ns
Aperture Uncertainty (Jitter, t
J
) Full 0.1 ps rms
Wake-Up Time
1
Full 500 μs
OUT-OF-RANGE RECOVERY TIME Full 2 Cycles
1
Wake-up time is dependent on the value of the decoupling capacitors.
SPI TIMING SPECIFICATIONS
Table 5.
Parameter Description Min Typ Max Unit
SPI TIMING REQUIREMENTS
t
DS
Setup time between the data and the rising edge of SCLK 2 ns
t
DH
Hold time between the data and the rising edge of SCLK 2 ns
t
CLK
Period of the SCLK 40 ns
t
S
Setup time between CSB and SCLK 2 ns
t
H
Hold time between CSB and SCLK 2 ns
t
HIGH
SCLK pulse width high 10 ns
t
LOW
SCLK pulse width low 10 ns
t
EN_SDIO
Time required for the SDIO pin to switch from an input
to an output relative to the SCLK falling edge
10 ns
t
DIS_SDIO
Time required for the SDIO pin to switch from an output
to an input relative to the SCLK rising edge
10 ns
Timing Diagram
M – 1
M + 1
M + 2
M + 5
M + 4
M + 3
M
N – 1
N + 1
N – 11 M – 10 N – 10 M – 9 N – 9 M – 8 N – 8 M – 7 N – 7
N + 2
N + 5
N + 4
N + 3
N
t
A
t
CH
t
CLK
t
DCO
t
SKEW
t
PD
VIN±A
VIN±B
CLK+
CLK–
DCO+, DCO–
CH A, CH B
DATA CH A, CH B
09085-002
Figure 2. Output Data Timing