Datasheet

Data Sheet AD9284
Rev. A | Page 5 of 24
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature, unless otherwise noted.
Table 3.
Parameter
1
Temperature Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance LVDS/PECL
Internal Common-Mode Bias Full 1.2 V
Differential Input Voltage
2
Full 0.2 6 V p-p
Input Voltage Range Full AVDD − 0.3 AVDD + 1.6 V
High Level Input Voltage Full 1.2 3.6 V
Low Level Input Voltage Full 0 0.8 V
High Level Input Current Full −10 +10 μA
Low Level Input Current Full −10 +10 μA
Input Resistance (Differential) 25°C 20 kΩ
Input Capacitance 25°C 4 pF
LOGIC INPUTS
CSB
High Level Input Voltage Full 1.2 DRVDD + 0.3 V
Low Level Input Voltage Full 0 0.8 V
High Level Input Current Full −5 −0.4 +5 μA
Low Level Input Current Full −80 −63 −50 μA
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF
SCLK, SDIO/PWDN,
OE
High Level Input Voltage Full 1.2 DRVDD + 0.3 V
Low Level Input Voltage Full 0 0.8 V
High Level Input Current Full 50 57 70 μA
Low Level Input Current Full −5 −0.4 +5 μA
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF
DIGITAL OUTPUTS (D7+, D7− to D0+, D0−), LVDS
DRVDD = 1.8 V
Differential Output Voltage (V
OD
) Full 290 345 400 mV
Output Offset Voltage (V
OS
) Full 1.15 1.25 1.35 V
Output Coding (Default) Offset binary
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were
completed.
2
Specified for LVDS and LVPECL only.