Datasheet

Data Sheet AD9284
Rev. A | Page 19 of 24
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 12 are not currently supported for this device.
Table 12. Memory Map Registers
Addr
(Hex)
Register
Name
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
Chip Configuration Registers
0x00 SPI port
configuration
0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 Nibbles are
mirrored so
that LSB-first
or MSB-first
mode
registers
correctly,
regardless of
shift mode
0x01 Chip ID
(global)
8-bit chip ID 0x0A Unique chip
ID used to
differentiate
devices; read
only
0x02 Chip grade
(global)
Open Speed grade ID
000 = 250 MSPS
Open 0x00 Unique speed
grade ID is
used to
differentiate
devices; read
only
Device Index and Transfer Registers
0x05
Device
Index A
Open
ADC B
default
ADC A
default
0xFF
Bits are set to
determine
which on-chip
device
receives the
next write
command;
default is all
devices on the
chip
0xFF Transfer Open Transfer 0xFF Synchronous
transfer of
data from the
master shift
register to
the slave
Program Registers (May or may not be indexed by device index)
0x08 Modes
(global)
Open Internal power-down mode
00: chip run
01: full power-down
10: reserved
11: reserved
0x00 Determines
various
generic
modes
of chip
operation
0x09 Clock
(global)
Open Clock
boost
Duty cycle
stabilizer
0x01
0x0D Test mode
(local)
Open Reset
PN23 gen
Reset
PN9 gen
Open Output test mode
000: off
001: midscale short
010: +FS short
011: −FS short
100: checkerboard output
101: PN23 sequence
110: PN9 sequence
111: one-/zero-word toggle
0x00 When test
mode is set,
test data is
placed on the
output pins
in place of
normal data
0x0E BIST (local) Open BIST init Open BIST enable 0x00 BIST mode
config