Datasheet

AD9279
Rev. 0 | Page 6 of 44
DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature, unless otherwise noted.
Table 2.
Parameter
1
Temperature Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Differential Input Voltage
2
Full 250 mV p-p
Input Common-Mode Voltage Full 1.2 V
Input Resistance (Differential) 25°C 20 kΩ
Input Capacitance 25°C 1.5 pF
CW 4LO INPUTS (4LO+, 4LO−)
Logic Compliance CMOS/LVDS/LVPECL
Differential Input Voltage
2
Full 250 mV p-p
Input Common-Mode Voltage Full 1.2 V
Input Resistance (Differential) 25°C 20 kΩ
Input Capacitance 25°C 1.5 pF
LOGIC INPUTS (PDWN, STBY, SCLK, SDIO)
Logic 1 Voltage Full 1.2 AVDD1 + 0.3 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 0.5 pF
LOGIC INPUTS (RESET)
Logic 1 Voltage Full 1.2 AVDD2 + 0.3 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 0.5 pF
LOGIC INPUT (CSB)
Logic 1 Voltage Full 1.2 AVDD1 + 0.3 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 70 kΩ
Input Capacitance 25°C 0.5 pF
LOGIC OUTPUT (SDIO)
3
Logic 1 Voltage (I
OH
= 800 A) Full 1.79 V
Logic 0 Voltage (I
OL
= 50 A) Full 0.05 V
DIGITAL OUTPUTS (DOUTx+, DOUTx−), (ANSI-644)
Logic Compliance LVDS
Differential Output Voltage (V
OD
) Full 247 454 mV
Output Offset Voltage (V
OS
) Full 1.125 1.375 V
Output Coding (Default) Offset binary
DIGITAL OUTPUTS (DOUTx+, DOUTx−),
(LOW POWER, REDUCED SIGNAL OPTION)
Logic Compliance LVDS
Differential Output Voltage (V
OD
) Full 150 250 mV
Output Offset Voltage (V
OS
) Full 1.10 1.30 V
Output Coding (Default) Offset binary
LOGIC OUTPUT (GPO0/GPO1/GPO2/GPO3)
Logic 0 Voltage (I
OL
= 50 A) Full 0.05 V
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2
Specified for LVDS and LVPECL only.
3
Specified for 13 SDIO pins sharing the same connection.