Datasheet

AD9279
Rev. 0 | Page 41 of 44
Addr.
(Hex)
Register Name
Bit 7
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Default
Value
Comments
0x0F FLEX_CHANNEL_
INPUT
Filter cutoff frequency control
0000 = 1.3 × 1/3 × f
SAMPLE
0001 = 1.2 × 1/3 × f
SAMPLE
0010 = 1.1 × 1/3 × f
SAMPLE
0011 = 1.0 × 1/3 × f
SAMPLE
(default)
0100 = 0.9 × 1/3 × f
SAMPLE
0101 = 0.8 × 1/3 × f
SAMPLE
0110 = 0.7 × 1/3 × f
SAMPLE
1000 = 1.3 × 1/4.5 × f
SAMPLE
1001 = 1.2 × 1/4.5 × f
SAMPLE
1010 = 1.1 × 1/4.5 × f
SAMPLE
1011 = 1.0 × 1/4.5 × f
SAMPLE
1100 = 0.9 × 1/4.5 × f
SAMPLE
1101 = 0.8 × 1/4.5 × f
SAMPLE
1110 = 0.7 × 1/4.5 × f
SAMPLE
X X X X 0x30 Antialiasing filter
cutoff (global).
0x10 FLEX_OFFSET X X 1 0 0 0 0 0 0x20 Reserved.
0x11 FLEX_GAIN X X X X PGA gain
00 = 21 dB
01 = 24 dB (default)
10 = 27 dB
11 = 30 dB
LNA gain
00 = 15.6 dB
01 = 17.9 dB
10 = 21.3 dB
(default)
0x06 LNA and PGA gain
adjustment
(global).
0x12 BIAS_CURRENT X X X X 1 X LNA bias
00 = high
01 = mid-high
(default)
10 = mid-low
11 = low
0x09 LNA bias current
adjustment
(global).
0x14 OUTPUT_MODE X 0 = LVDS
ANSI-644
(default)
1 = LVDS
low power,
(IEEE
1596.3
similar)
X X X Output
invert
enable
1 = on
0 = off
(default)
Data format select
00 = offset binary
(default)
01 = twos
complement
0x00 Configures the
outputs and the
format of the data
(Bits[7:3] and
Bits[1:0] are global;
Bit 2 is local).
0x15 OUTPUT_ADJUST X X Output driver
termination
00 = none (default)
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
X X X DCO±
and
FCO±
2× drive
strength
1 = on
0 = off
(default)
0x00 Determines LVDS
or other output
properties.
Primarily functions
to set the LVDS
span and
common-mode
levels in place of
an external resistor
(Bits[7:1] are global;
Bit 0 is local).
0x16 OUTPUT_PHASE X X X X Output clock phase adjust
0000 = 0° relative to data edge
0001 = 60° relative to data edge
0010 = 120° relative to data edge
0011 = 180° relative to data edge (default)
0100 = reserved
0101 = 300° relative to data edge
0110 = 360° relative to data edge
0111 = reserved
1000 = 480° relative to data edge
1001 = 540° relative to data edge
1010 = 600° relative to data edge
1011 to 1111 = 660° relative to data edge
0x03 On devices that
use global clock
divide, deter-
mines which
phase of the
divider output is
used to supply
the output clock.
Internal latching
is unaffected.
(global)
0x18 FLEX_VREF X 0 =
internal
reference
1 =
external
reference
X X X X 1 1 0x03 Select internal
reference
(recommended
default) or
external reference
(global).
0x19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-Defined
Pattern 1, LSB
(global).