Datasheet

AD9279
Rev. 0 | Page 38 of 44
This interface is flexible enough to be controlled by either serial
PROMs or PIC microcontrollers, providing the user with
an alternative method, other than a full SPI controller, for
programming the device (see the AN-812 Application Note).
DON’T
CARE
DON’T
CARE
DON’T
CARE
DON’T
CARE
SDIO
SCLK
CSB
t
S
t
DH
t
HIGH
t
CLK
t
LOW
t
DS
t
H
R/W W1 W0 A12 A11 A10 A9 A8 A7
D5 D4 D3 D2 D1 D0
09423-069
Figure 69. Serial Timing Details
Table 18. Serial Timing Definitions
Parameter Timing (ns min) Description
t
DS
5 Setup time between the data and the rising edge of SCLK
t
DH
2 Hold time between the data and the rising edge of SCLK
t
CLK
40 Period of the clock
t
S
5 Setup time between CSB and SCLK
t
H
2 Hold time between CSB and SCLK
t
HIGH
16 Minimum period that SCLK should be in a logic high state
t
LOW
16 Minimum period that SCLK should be in a logic low state
t
EN_SDIO
10
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling
edge (not shown in Figure 69)
t
DIS_SDIO
10
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising
edge (not shown in Figure 69)