Datasheet

AD9279
Rev. 0 | Page 32 of 44
Two output clocks are provided to assist in capturing data from
the AD9279. DCO± is used to clock the output data and is equal
to six times the sampling clock rate. Data is clocked out of the
AD9279 and must be captured on the rising and falling edges
of DCO±, which supports double data rate (DDR) capturing.
The frame clock output (FCO±) is used to signal the start of a
new output byte and is equal to the sampling clock rate. See the
timing diagram shown in Figure 2 for more information.
An 8-, 10-, or 14-bit serial stream can also be initiated from the
SPI. This allows the user to implement different serial streams and
to test device compatibility with lower and higher resolution
systems. When changing the resolution to an 8- or 10-bit serial
stream, the data stream is shortened. When using the 14-bit
option, the data stream stuffs two 0s at the end of the normal
12-bit serial data.
When using the SPI, all of the data outputs can also be inverted
from their nominal state by setting Bit 2 in the OUTPUT_MODE
register (Address 0x14). This is not to be confused with inverting
the serial stream to an LSB first mode. In default mode, as shown
in Figure 2, the MSB is represented first in the data output serial
stream. However, this order this can be inverted so that the LSB is
represented first in the data output serial stream (see Figure 3).
There are 12 digital output test pattern options available that
can be initiated through the SPI. This feature is useful when
validating receiver capture and timing. See Table 13 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various
ways, depending on the test pattern chosen. Note that some
patterns may not adhere to the data format select option. In
addition, custom user-defined test patterns can be assigned in
the user pattern registers (Address 0x19 through Address 0x1C).
All test mode options except PN sequence short and PN sequence
long can support 8- to 14-bit word lengths to verify data capture
to the receiver.
The PN sequence short pattern produces a pseudo random
bit sequence that repeats itself every 2
9
− 1 bits, or 511 bits. A
description of the PN sequence short and how it is generated
can be found in Section 5.1 of the ITU-T O.150 (05/96) standard.
The only difference is that the starting value is a specific value
instead of all 1s (see Table 14 for the initial values).
Table 13. Flexible Output Test Modes
1
Output Test Mode
Bit Sequence Pattern Name Digital Output Word 1 Digital Output Word 2
Subject to Data
Format Select
0000 Off (default) N/A N/A N/A
0001 Midscale short 1000 0000 0000 Same Yes
0010 +Full-scale short 1111 1111 1111 Same Yes
0011 −Full-scale short 0000 0000 0000 Same Yes
0100 Checkerboard 1010 1010 1010 0101 0101 0101 No
0101 PN sequence long N/A N/A Yes
0110 PN sequence short N/A N/A Yes
0111 One-/zero-word toggle 1111 1111 1111 0000 0000 0000 No
1000 User input Register 0x19 and Register 0x1A Register 0x1B and Register 0x1C No
1001 1-/0-bit toggle 1010 1010 1010 N/A No
1010 1× sync 0000 0011 1111 N/A No
1011 One bit high 1000 0000 0000 N/A No
1100 Mixed bit frequency 1010 0011 0011 N/A No
1
N/A is not applicable.