Datasheet

AD9279
Rev. 0 | Page 12 of 44
Pin No. Name Description
B10 LG-B LNA Ground for Channel B
A10 LI-B LNA Analog Input for Channel B
D10 LOSW-B LNA Analog Switched Output for Channel B
C10 LO-B LNA Analog Inverted Output for Channel B
B11 LG-C LNA Ground for Channel C
A11 LI-C LNA Analog Input for Channel C
D11 LOSW-C LNA Analog Switched Output for Channel C
C11 LO-C LNA Analog Inverted Output for Channel C
B12 LG-D LNA Ground for Channel D
A12 LI-D LNA Analog Input for Channel D
D12 LOSW-D LNA Analog Switched Output for Channel D
C12 LO-D LNA Analog Inverted Output for Channel D
K10 GPO0 General Purpose Open Drain Output 0
J10 GPO1 General Purpose Open Drain Output 1
K9 GPO2 General Purpose Open Drain Output 2
J9 GPO3 General Purpose Open Drain Output 3
K8 RESET Reset for Synchronizing 4LO Divide-by-4 Counter
K7 4LO− CW Doppler 4LO Input Complement
J7 4LO+ CW Doppler 4LO Input True
A8 GAIN− Gain Control Voltage Input Complement
A7 GAIN+ Gain Control Voltage Input True
A6 RBIAS External Resistor to Set the Internal ADC Core Bias Current
A5 VREF Voltage Reference Input/Output
K5 CWI− CW Doppler I Output Complement
J5 CWI+ CW Doppler I Output True
K3 CWQ− CW Doppler Q Output Complement
J3 CWQ+ CW Doppler Q Output True
C1 LO-E LNA Analog Inverted Output for Channel E
D1 LOSW-E LNA Analog Switched Output for Channel E