Datasheet

AD9277
Rev. 0 | Page 8 of 48
SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f
IN
= 5 MHz, full temperature, unless otherwise noted.
Table 3.
Parameter
1
Temperature Min Typ Max Unit
CLOCK
2
Clock Rate Full 10 50 MHz
Clock Pulse Width High (t
EH
) Full 10 ns
Clock Pulse Width Low (t
EL
) Full 10 ns
OUTPUT PARAMETERS
2, 3
Propagation Delay (t
PD
) Full (t
SAMPLE
/2) + 1.5 (t
SAMPLE
/2) + 2.3 (t
SAMPLE
/2) + 3.1 ns
Rise Time (t
R
) (20% to 80%) Full 300 ps
Fall Time (t
F
) (20% to 80%) Full 300 ps
FCO Propagation Delay (t
FCO
) Full (t
SAMPLE
/2) + 1.5 (t
SAMPLE
/2) + 2.3 (t
SAMPLE
/2) + 3.1 ns
DCO Propagation Delay (t
CPD
)
4
Full t
FCO
+ (t
SAMPLE
/24) ns
DCO to Data Delay (t
DATA
)
4
Full (t
SAMPLE
/24) − 300 (t
SAMPLE
/24) (t
SAMPLE
/24) + 300 ps
DCO to FCO Delay (t
FRAME
)
4
Full (t
SAMPLE
/24) − 300 (t
SAMPLE
/24) (t
SAMPLE
/24) + 300 ps
Data-to-Data Skew (t
DATA-MAX
− t
DATA-MIN
) Full ±100 ±350 ps
Wake-Up Time (Standby), GAIN+ = 0.5 V 25°C 2 µs
Wake-Up Time (Power-Down) 25°C 1 ms
Pipeline Latency Full 8
Clock
cycles
APERTURE
Aperture Uncertainty (Jitter) 25°C <1 ps rms
LO GENERATION
4LO Frequency Full 4 40 MHz
LO Divider RESET Setup Time
5
Full 5 ns
LO Divider RESET Hold Time
5
Full 5 ns
LO Divider RESET High Pulse Width Full 20 ns
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2
Can be adjusted via the SPI.
3
Measurements were made using a part soldered to FR-4 material.
4
t
SAMPLE
/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
5
RESET edge to rising 4LO edge.