Datasheet

AD9277
Rev. 0 | Page 42 of 48
Table 18. AD9277 Memory Map Registers
Addr.
(Hex) Register Name
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Default
Value Comments
Chip Configuration Registers
0x00 chip_port_config 0 LSB first
1 = on
0 = off
(default)
Soft
reset
1 = on
0 = off
(default)
1 1 Soft
reset
1 = on
0 = off
(default)
LSB first
1 = on
0 = off
(default)
0 0x18 Nibbles should be
mirrored so that
LSB or MSB first
mode is set cor-
rectly regardless of
shift mode.
0x01 chip_id Chip ID Bits[7:0]
(AD9277 = 0x73, default)
Default is unique
chip ID, different
for each device.
Read-only register.
0x02 chip_grade X X Child ID[5:4]
(identify device
variants of chip ID)
00 = 40 MSPS
(default)
01 = 50 MSPS
X X X X 0x00 Child ID used to
differentiate ADC
speed power
modes.
Device Index and Transfer Registers
0x04 device_index_2 X X X X Data
Channel
H
1 = on
(default)
0 = off
Data
Channel
G
1 = on
(default)
0 = off
Data
Channel
F
1 = on
(default)
0 = off
Data
Channel
E
1 = on
(default)
0 = off
0x0F Bits are set to
determine which
on-chip device
receives the next
write command.
0x05 device_index_1 X X Clock
Channel
DCO±
1 = on
0 = off
(default)
Clock
Channel
FCO±
1 = on
0 = off
(default)
Data
Channel
D
1 = on
(default)
0 = off
Data
Channel
C
1 = on
(default)
0 = off
Data
Channel
B
1 = on
(default)
0 = off
Data
Channel
A
1 = on
(default)
0 = off
0x0F Bits are set to
determine which
on-chip device
receives the next
write command.
0xFF device_update X X X X X X X SW
transfer
1 = on
0 = off
(default)
0x00 Synchronously
transfers data
from the master
shift register to
the slave.
Program Function Registers
0x08 modes X X X LNA
input
imped-
ance
1 = 5 kΩ
0 = 15 kΩ
(default)
0 Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
100 = CW mode (TGC PDWN)
0x00 Determines
generic modes
of chip operation
(global).
0x09 clock X X X X X X X DCS
1 = on
(default)
0 = off
0x01 Turns the internal
duty cycle stabilizer
(DCS) on and off
(global).
0x0D test_io User test mode
00 = off (default)
01 = on, single
alternate
10 = on, single once
11 = on, alternate once
Reset PN
long
gen
1 = on
0 = off
(default)
Reset PN
short
gen
1 = on
0 = off
(default)
Output test mode—see Table 13
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checkerboard output
0101 = PN sequence long
0110 = PN sequence short
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency (format
determined by output_mode)
0x00 When this register
is set, the test data
is placed on the
output pins in
place of normal
data. (Local, except
for PN sequence.)
0x0E GPO outputs X X X X General-purpose digital outputs 0x00 Values placed on
GPO[0:3] pins
(global).