Datasheet

AD9277
Rev. 0 | Page 37 of 48
600
–400
400
–200
200
–600
0
–1.5ns –0.5ns–1.0ns 0ns 0.5ns 1.0ns 1.5ns
EYE DIAGRAM VOLTAGE (V)
EYE: ALL BITS
ULS: 2396/2396
25
0
5
10
15
20
–200ps –100ps 0ps 100ps 200ps
TIE JITTER HISTOGRAM (Hits)
08181-069
Two output clocks are provided to assist in capturing data from
the AD9277. DCO± is used to clock the output data and is equal
to six times the sampling clock rate. Data is clocked out of the
AD9277 and must be captured on the rising and falling edges
of DCO±, which supports double data rate (DDR) capturing.
The frame clock output (FCO±) is used to signal the start of a
new output byte and is equal to the sampling clock rate. See the
timing diagram shown in Figure 2 for more information.
When using the serial port interface (SPI), the DCO± phase
can be adjusted in 60° increments relative to the data edge. This
enables the user to refine system timing margins if required. The
default DCO± timing, as shown in Figure 2, is 180° relative to
the output data edge.
An 8-, 10-, or 12-bit serial stream can also be initiated from the
SPI. This allows the user to implement different serial streams and
to test the device’s compatibility with lower and higher resolution
systems. When changing the resolution to an 8-, 10-, or 12-bit
serial stream, the data stream is shortened.
When using the SPI, all of the data outputs can also be inverted
from their nominal state by setting Bit 2 in the output mode
register (Address 0x14). This is not to be confused with inverting
the serial stream to an LSB first mode. In default mode, as shown
in Figure 2, the MSB is represented first in the data output serial
stream. However, this order can be inverted so that the LSB is
represented first in the data output serial stream (see Figure 3).
There are 14 digital output test pattern options available that
can be initiated through the SPI. This feature is useful when
validating receiver capture and timing. Refer to Table 13 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various
ways, depending on the test pattern chosen. Note that some
patterns may not adhere to the data format select option. In
addition, custom user-defined test patterns can be assigned in
the user pattern registers (Address 0x19 through Address 0x1C).
All test mode options except PN sequence short and PN sequence
long can support 8- to 14-bit word lengths in order to verify
data capture to the receiver.
Figure 75. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω
Termination On and Trace Lengths of Greater Than 24 Inches on Standard FR-4
The format of the output data is offset binary by default. Table 12
provides an example of the output coding format. To change the
output data format to twos complement, see the Memory Map
section.
Table 12. Digital Output Coding
Code
(V
IN+
) − (V
IN−
),
Input Span = 2 V p-p (V)
Digital Output
Offset Binary (D13 to D0)
16383 +1.00 11 1111 1111 1111
8192 0.00 10 0000 0000 0000
8191 −0.000488 01 1111 1111 1111
0 −1.00 00 0000 0000 0000
The PN sequence short pattern produces a pseudorandom
bit sequence that repeats itself every 2
9
− 1 bits, or 511 bits. A
description of the PN sequence short and how it is generated
can be found in Section 5.1 of the ITU-T O.150 (05/96) standard.
The only difference is that the starting value is a specific value
instead of all 1s (see Table 14 for the initial values).
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 14 bits
times the sample clock rate, with a maximum of 700 Mbps
(14 bits × 50 MSPS = 700 Mbps). The lowest typical conversion
rate is 10 MSPS, but the PLL can be set up for encode rates as
low as 5 MSPS via the SPI if lower sample rates are required
for a specific application. See Table 18 for details on enabling
this feature.