Octal LNA/VGA/AAF/14-Bit ADC and CW I/Q Demodulator AD9277 FEATURES APPLICATIONS 8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator Low noise preamplifier (LNA) Input-referred noise: 0.75 nV/√Hz typical at 5 MHz (gain = 21.3 dB) SPI-programmable gain: 15.6 dB/17.9 dB/21.3 dB Single-ended input: VIN maximum = 733 mV p-p/ 550 mV p-p/367 mV p-p Dual-mode active input impedance matching Bandwidth (BW) > 100 MHz Full-scale (FS) output: 4.
AD9277 TABLE OF CONTENTS Features .............................................................................................. 1 Ultrasound .................................................................................. 21 Applications ....................................................................................... 1 Channel Overview ..................................................................... 22 Product Highlights ....................................................................
AD9277 GENERAL DESCRIPTION The AD9277 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA); an antialiasing filter (AAF); a 14-bit, 10 MSPS to 50 MSPS analog-todigital converter (ADC); and an I/Q demodulator with programmable phase rotation.
AD9277 SPECIFICATIONS AC SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, RS = 50 Ω, LNA gain = 21.3 dB, LNA bias = high, PGA gain = 24 dB, GAIN− = 0.8 V, AAF LPF cutoff = fSAMPLE/4.5, HPF cutoff = LPF cutoff/20.7 (default), fSAMPLE = 50 MSPS (Register 0x02 = 0x01), full temperature, ANSI-644 LVDS mode, unless otherwise noted. Table 1.
AD9277 Parameter 1 Noise Figure Active Termination Matched Unterminated Correlated Noise Ratio Output Offset Signal-to-Noise Ratio (SNR) Harmonic Distortion Second Harmonic Third Harmonic Two-Tone Intermodulation (IMD3) Channel-to-Channel Crosstalk Channel-to-Channel Delay Variation PGA Gain GAIN ACCURACY Gain Law Conformance Error Linear Gain Error Channel-to-Channel Matching GAIN CONTROL INTERFACE Normal Operating Range Gain Range Scale Factor Response Time GAIN+ Impedance GAIN− Impedance CW DOPPLER M
AD9277 Parameter 1 Noise Figure Input-Referred Dynamic Range Output-Referred SNR Two-Tone Intermodulation (IMD3) Quadrature Phase Error I/Q Amplitude Imbalance Channel-to-Channel Matching POWER SUPPLY AVDD1 AVDD2 DRVDD IAVDD1 Test Conditions/Comments RS = 50 Ω, RFB = ∞ LNA gain = 15.6 dB LNA gain = 17.9 dB LNA gain = 21.3 dB RS = 0 Ω, RFB = ∞ LNA gain = 15.6 dB LNA gain = 17.9 dB LNA gain = 21.3 dB −3 dBFS input, fRF = 2.5 MHz, f4LO = 10 MHz, 1 kHz offset fRF1 = 5.015 MHz, fRF2 = 5.
AD9277 DIGITAL SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted. Table 2.
AD9277 SWITCHING SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted. Table 3.
AD9277 ADC TIMING DIAGRAMS N–1 AIN N tEH CLK– tEL CLK+ tCPD DCO– DCO+ tFCO tFRAME FCO– FCO+ tPD tDATA MSB N–8 D12 N–8 D11 N–8 D10 N–8 D9 N–8 D8 N–8 D7 N–8 D6 N–8 D5 N–8 D4 N–8 D3 N–8 D2 N–8 D1 N–8 D0 N–8 MSB N–7 D12 N–7 D7 N–8 D8 N–8 D9 N–8 D10 N–8 D11 N–8 D12 N–8 LSB N–7 D0 N–7 DOUTx+ 08181-002 DOUTx– Figure 2.
AD9277 ABSOLUTE MAXIMUM RATINGS Table 4.
AD9277 76 LOSW-D 77 LO-D PIN 1 INDICATOR LI-E 1 75 LI-D LG-E 2 74 LG-D AVDD2 3 73 AVDD2 AVDD1 4 72 AVDD1 71 LO-C 70 LOSW-C LI-F 7 69 LI-C LG-F 8 68 LG-C AVDD2 9 67 AVDD2 AVDD1 10 66 AVDD1 LO-G 11 65 LO-B 64 LOSW-B 63 LI-B LG-G 14 62 LG-B AVDD2 15 61 AVDD2 AVDD1 16 60 AVDD1 LO-H 17 59 LO-A LOSW-H 18 58 LOSW-A LI-H 19 57 LI-A LG-H 20 56 LG-A AVDD2 21 55 AVDD2 AVDD1 22 54 AVDD1 CLK– 23 53 CSB CLK+ 24 52 SDIO AVDD1 25 51 SCLK EXPOSED PADD
AD9277 Pin No.
AD9277 Pin No. 89 90 92 93 94 95 99 100 Name RBIAS VREF CWI− CWI+ CWQ− CWQ+ LO-E LOSW-E Description External Resistor to Set the Internal ADC Core Bias Current. Voltage Reference Input/Output. CW Doppler I Output Complement. CW Doppler I Output True. CW Doppler Q Output Complement. CW Doppler Q Output True. LNA Analog Inverted Output for Channel E. LNA Analog Switched Output for Channel E. Rev.
AD9277 TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE fSAMPLE = 50 MSPS, fIN = 5 MHz, RS = 50 Ω, LNA gain = 21.3 dB, LNA bias = high, PGA gain = 24 dB, AAF LPF cutoff = fSAMPLE/4.5, HPF cutoff = LPF cutoff/20.7 (default). 2.0 25 PERCENTAGE OF UNITS (%) 1.5 GAIN ERROR (dB) 1.0 –40°C 0.5 +25°C 0 +85°C –0.5 –1.0 20 15 10 5 –1.5 0.6 0.8 1.0 GAIN+ (V) 1.2 1.4 1.6 0 GAIN ERROR (dB) Figure 8. Gain Error Histogram, GAIN+ = 1.
AD9277 180,000 –126 NUMBER OF HITS 140,000 120,000 100,000 80,000 60,000 40,000 20,000 –8 –6 –4 –2 0 2 CODES 4 6 8 10 12 –130 LNA GAIN = 21.3dB –132 LNA GAIN = 17.9dB –134 LNA GAIN = 15.6dB –136 –138 –140 –142 08181-011 0 –12 –10 –128 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 GAIN+ (V) Figure 11. Output-Referred Noise Histogram, GAIN+ = 0.0 V 08181-014 OUTPUT-REFERRED NOISE (dBFS/Hz) 160,000 Figure 14. Short-Circuit, Output-Referred Noise vs.
0 –10 –20 –30 –40 GAIN+ = 0.4V –50 GAIN+ = 1.0V –60 –70 GAIN+ = 1.6V –80 –90 0 2 4 6 8 10 12 INPUT FREQUENCY (MHz) 14 16 –40 –60 GAIN+ = 0V –80 GAIN+ = 0.8V –10 –10 –20 –20 –30 –30 IMD3 (dBFS) 0 GAIN+ = 0.4V –50 GAIN+ = 1.6V –40 –10 –5 0 fIN2 = fIN1 + 0.01MHz fIN1 = –1dBFS, fIN2 = –21dBFS –40 –50 8MHz –70 2.3MHz 5MHz –70 GAIN+ = 1.0V 2 4 6 8 10 12 INPUT FREQUENCY (MHz) 14 16 –90 0.4 0.6 0.8 1.0 GAIN+ (V) 1.2 1.4 1.6 08181-022 0 –80 08181-019 –80 Figure 18.
AD9277 CW DOPPLER MODE fRF = 2.5 MHz at −3 dBFS, f4LO = 10 MHz, RS = 50 Ω, LNA gain = 21.3 dB, LNA bias = high, all CW channels enabled, phase rotation 0°. 175 1.0 0.8 DYNAMIC RANGE (dBFS/ Hz) 170 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 CH A + B + C + D + E + F + G + H CH A + B + C + D 165 CH A + B CH A 160 155 150 –1.2 100 1k 10k BASEBAND FREQUENCY (Hz) 145 0 Figure 23. Quadrature Phase Error vs. Baseband Frequency Figure 26. Small-Signal Dynamic Range 0.10 12 0.08 10 0.
AD9277 170 166 LNA GAIN = 15.6dB 164 LNA GAIN = 17.9dB 162 LNA GAIN = 21.3dB 160 158 156 154 1 2 3 4 5 RF FREQUENCY (MHz) 6 7 8 9 10 08181-079 DYNAMIC RANGE (dB) 168 Figure 29. Small-Signal Dynamic Range vs. RF Frequency Rev.
AD9277 EQUIVALENT CIRCUITS VCM AVDD2 AVDD 15kΩ LI-x, LG-x 350Ω 08181-024 SDIO Figure 30. Equivalent LNA Input Circuit 08181-028 30kΩ Figure 34. Equivalent SDIO Input Circuit DRVDD AVDD2 DRVDD 10Ω V V V V DOUTx– 08181-025 LO-x, LOSW-x DRVDD DOUTx+ DRVDD DRVDD 08181-029 AVDD2 DRGND Figure 31. Equivalent LNA Output Circuit Figure 35. Equivalent Digital Output Circuit AVDD1 350Ω CLK+ AVDD1 10kΩ SCLK, PDWN, OR STBY 1.
AD9277 AVDD1 70kΩ 50Ω GAIN+ 08181-033 08181-035 350Ω CSB AVDD2 AVDD1 Figure 38. Equivalent CSB Input Circuit Figure 41. Equivalent GAIN+ Input Circuit 0.8V AVDD2 VREF 70kΩ 08181-036 08181-034 6kΩ 50Ω GAIN– Figure 42. Equivalent GAIN− Input Circuit Figure 39. Equivalent VREF Circuit AVDD2 08181-037 Figure 43. Equivalent CWI±, CWQ± Output Circuit 08181-032 AVDD2 Figure 40. Equivalent RBIAS Circuit GPOx 10Ω 08181-038 RBIAS CWx+, CWx– 100Ω Figure 44.
AD9277 THEORY OF OPERATION Most modern ultrasound machines use digital beamforming. In this technique, the signal is converted to digital format immediately following the TGC amplifier, and then beamforming is accomplished digitally. ULTRASOUND The primary application for the AD9277 is medical ultrasound. Figure 45 shows a simplified block diagram of an ultrasound system. A critical function of an ultrasound system is the time gain control (TGC) compensation for physiological signal attenuation.
AD9277 4 4LO– 4LO+ LO GENERATION RESET RFB1 LO-x RFB2 LOSW-x T/R SWITCH C S CWQ+ CWQ– LI-x LG-x CSH CLG TRANSDUCER CWI+ CWI– LNA 15.6dB, 17.9dB, 21.3dB ATTENUATOR –42dB TO 0dB POST AMP PIPELINE ADC AAF DOUTx+ SERIAL LVDS DOUTx– 21dB, 24dB, 27dB, 30dB GAIN INTERPOLATOR X-AMP VGA GAIN– 08181-040 GAIN+ Figure 46. Simplified Block Diagram of a Single Channel CFB CHANNEL OVERVIEW VO+ Each channel contains both a TGC signal path and a CW Doppler signal path.
AD9277 The LNA consists of a single-ended voltage gain amplifier with differential outputs and the negative output externally available. For example, with a fixed gain of 8× (17.9 dB), an active input termination is synthesized by connecting a feedback resistor between the negative output pin, LO-x, and the positive input pin, LI-x. This well-known technique is used for interfacing multiple probe impedances to a single system. The input resistance is shown in Equation 1.
AD9277 LNA Noise The short-circuit noise voltage (input-referred noise) is an important limit on system performance. The short-circuit noise voltage for the LNA is 0.75 nV/√Hz at a gain of 21.3 dB, including the VGA noise at a VGA postamp gain of 27 dB. These measurements, which were taken without a feedback resistor, provide the basis for calculating the input noise and noise figure (NF) performance of the configurations shown in Figure 49. + 12.0 10.5 VOUT – NOISE FIGURE (dB) 9.
AD9277 INPUT OVERDRIVE CW DOPPLER OPERATION Excellent overload behavior is of primary importance in ultrasound. Both the LNA and VGA have built-in overdrive protection and quickly recover after an overload event. Each channel of the AD9277 includes an I/Q demodulator. Each demodulator has an individual programmable phase shifter. The I/Q demodulator is ideal for phased array beamforming applications in medical ultrasound. Each channel can be programmed for 16 delay states (360°/16 or 22.
AD9277 I/Q Demodulator and Phase Shifter Dynamic Range and Noise The I/Q demodulators consist of double-balanced passive mixers. The RF input signals are converted into currents by transconductance stages that have a maximum differential input signal capability matching the LNA output full scale. These currents are then presented to the mixers, which convert them to baseband (RF − LO) and twice RF (RF + LO). The signals are phase shifted according to the codes programmed into the SPI latch (see Table 8).
AD9277 CFILT OTHER RFILT AD9277s CWI+ AD8021 CHANNEL A 1.5V LNA I 18-BIT ADC Q 18-BIT ADC 1.5V AD8021 CWI– RFILT CFILT CFILT RFILT CWQ+ AD8021 1.5V 1.5V CHANNEL H LNA CWQ– AD8021 RFILT CFILT 4 08181-047 4LO– 4LO+ RESET LO GENERATION Figure 53.
AD9277 For CW Doppler operation, the AD9277 integrates the LNA, phase shifter, frequency conversion, and I/Q demodulation into a single package and directly yields the baseband signal. Figure 54 is a simplified diagram showing the concept for four channels. The ultrasound wave (US wave) is received by four transducer elements, TE1 through TE4, in an ultrasound probe and generates signals E1 through E4. In this example, the phase at TE1 leads the phase at TE2 by 45°.
AD9277 TGC OPERATION The TGC signal path is fully differential throughout to maximize signal swing and reduce even-order distortion; however, the LNAs are designed to be driven from a single-ended signal source. Gain values are referenced from the single-ended LNA input to the differential ADC input. A simple exercise in understanding the maximum and minimum gain requirements is shown in Figure 55. The maximum gain required is determined by (ADC Noise Floor/LNA Input Noise Floor) + Margin = 20 log(224/3.
AD9277 Table 10. Sensitivity and Dynamic Range Trade-Offs 1, 2, 3 LNA VGA Gain (V/V) 6 (dB) 15.6 Full-Scale Input (V p-p) 0.733 Input Noise (nV/√Hz) 0.98 8 17.9 0.550 0.86 12 21.3 0.367 0.75 Postamp Gain (dB) 21 24 27 30 21 24 27 30 21 24 27 30 Channel Typical Output Dynamic Range (dB) GAIN+ = 0 V 68.9 67.4 65.3 62.8 68.9 67.4 65.3 62.8 68.9 67.4 65.3 62.8 4 GAIN+ = 1.6 V 65.8 63.4 60.8 57.9 65.1 62.7 60.0 57.1 63.7 61.1 58.3 55.4 5 Input-Referred Noise 6 @ GAIN+ = 1.6 V (nV/√Hz) 1.312 1.
AD9277 0.6 PGA GAIN = 21dB 0.4 PGA GAIN = 24dB 0.3 0.2 0.1 PGA GAIN = 27dB 0 0.2 0.4 0.6 0.8 1.0 GAIN+ (V) 1.2 1.4 1.6 08181-051 PGA GAIN = 30dB 0 The input stages of the X-AMP are distributed along the ladder, and a biasing interpolator, controlled by the gain interface, determines the input tap point. With overlapping bias currents, signals from successive taps merge to provide a smooth attenuation range from −42 dB to 0 dB.
AD9277 100Ω 0.01µF GAIN– AD8138 100Ω 0.01µF 499Ω 31.3kΩ ±0.8V DC 0.8V CM 523Ω 50Ω 10kΩ ±0.4V DC AT 0.8V CM 08181-055 GAIN+ ±0.4V DC AT 0.8V CM 499Ω Figure 61. Differential GAIN+, GAIN− Pin Configuration VGA Noise In a typical application, a VGA compresses a wide dynamic range input signal to within the input span of an ADC.
AD9277 ADC 3.3V 50Ω * VFAC3 OUT The AD9277 uses a pipelined ADC architecture. The quantized output from each stage is combined into a 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on preceding samples. Sampling occurs on the rising edge of the clock.
AD9277 300 CURRENT (mA) 250 Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated as follows: SNR Degradation = 20 × log10(1/2 × π × fA × tJ) 200 150 100 IDRVDD 50 In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter.
AD9277 By asserting the STBY pin high, the AD9277 is placed into a standby mode. In this state, the device typically dissipates 200 mW. During standby, the entire part is powered down except for the internal references. The LVDS output drivers are placed into a high impedance state. This mode is well suited for applications that require power savings because it allows the device to be powered down when not in use and then quickly powered up. The time to power the device back up is also greatly reduced.
AD9277 600 400 EYE: ALL BITS 200 100 0 –100 –200 –400 ULS: 2399/2399 200 100 0 –100 –200 –300 –1.0ns –0.5ns 0ns 0.5ns 1.0ns –400 1.5ns 25 20 20 TIE JITTER HISTOGRAM (Hits) 25 15 10 5 0 –200ps –100ps 0ps 100ps 200ps Figure 73. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Less Than 24 Inches on Standard FR-4 –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns 15 10 5 0 –200ps –100ps 0ps 100ps 200ps 08181-068 –1.
AD9277 600 EYE: ALL BITS Two output clocks are provided to assist in capturing data from the AD9277. DCO± is used to clock the output data and is equal to six times the sampling clock rate. Data is clocked out of the AD9277 and must be captured on the rising and falling edges of DCO±, which supports double data rate (DDR) capturing. The frame clock output (FCO±) is used to signal the start of a new output byte and is equal to the sampling clock rate.
AD9277 Table 13.
AD9277 SERIAL PORT INTERFACE (SPI) The AD9277 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. The SPI offers the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, as documented in the Memory Map section.
AD9277 In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame.
AD9277 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index and transfer register map (Address 0x04 to Address 0xFF), and the program register map (Address 0x08 to Address 0x2D). The leftmost column of the memory map indicates the register address, and the default value is shown in the second rightmost column.
AD9277 Table 18. AD9277 Memory Map Registers Addr.
AD9277 Addr. (Hex) 0x0F Register Name flex_channel_input Bit 7 Bit 0 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) X X X X Filter cutoff frequency control 0000 = 1.3 × 1/3 × fSAMPLE 0001 = 1.2 × 1/3 × fSAMPLE 0010 = 1.1 × 1/3 × fSAMPLE 0011 = 1.0 × 1/3 × fSAMPLE (default) 0100 = 0.9 × 1/3 × fSAMPLE 0101 = 0.8 × 1/3 × fSAMPLE 0110 = 0.7 × 1/3 × fSAMPLE 1000 = 1.3 × 1/4.5 × fSAMPLE 1001 = 1.2 × 1/4.5 × fSAMPLE 1010 = 1.1 × 1/4.5 × fSAMPLE 1011 = 1.0 × 1/4.5 × fSAMPLE 1100 = 0.9 × 1/4.5 × fSAMPLE 1101 = 0.
AD9277 Addr.
AD9277 APPLICATIONS INFORMATION POWER AND GROUND RECOMMENDATIONS When connecting power to the AD9277, it is recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one 1.8 V supply is available, it should be routed to the AVDD1 pin first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD pin.
AD9277 OUTLINE DIMENSIONS 0.75 0.60 0.45 16.00 BSC SQ 1.20 MAX 14.00 BSC SQ 76 75 100 1 76 75 100 1 PIN 1 EXPOSED PAD TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY 51 25 26 50 BOTTOM VIEW (PINS UP) 51 26 0.50 BSC LEAD PITCH VIEW A 25 50 VIEW A 0.27 0.22 0.17 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
AD9277 NOTES Rev.
AD9277 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08181-0-7/09(0) Rev.
