Datasheet

AD9273
Rev. B | Page 10 of 48
ADC TIMING DIAGRAMS
DCO–
DCO+
DOUTx–
DOUTx+
FCO–
FCO+
AIN
CLK–
CLK+
MSB
N – 8
D10
N – 8
D9
N – 8
D8
N – 8
D7
N – 8
D6
N – 8
D5
N – 8
D4
N – 8
D3
N – 8
D2
N – 8
D1
N – 8
D0
N – 8
D10
N – 7
MSB
N – 7
N – 1
N
t
DATA
t
FRAME
t
FCO
t
PD
t
CPD
t
EH
t
EL
07030-002
Figure 2. 12-Bit Data Serial Stream (Default)
DCO–
DCO+
DOUTx–
DOUTx+
FCO–
FCO+
AIN
CLK–
CLK+
D0
(LSB)
D1
N – 8
D2
N – 8
D3
N – 8
D4
N – 8
D5
N – 8
D6
N – 8
D7
N – 8
D8
N – 8
D9
N – 8
D10
N – 8
D11
(MSB)
N – 1
N
t
DATA
t
FRAME
t
FCO
t
PD
t
CPD
t
EH
t
EL
07030-004
Figure 3. 12-Bit Data Serial Stream, LSB First