Datasheet

AD9272
Rev. C | Page 39 of 44
07029-113
NUMBER OF SDIO PINS CONNECTED TOGETHER
V
OH
(V)
1.715
1.720
1.725
1.730
1.735
1.740
1.745
1.750
1.755
1.760
1.765
1.770
1.775
1.780
1.785
1.790
1.795
1.800
0302010 40 50 60 70 80 90 100
Figure 68. SDIO Pin Loading
This interface is flexible enough to be controlled by either serial
PROMS or PIC mirocontrollers. This provides the user with
an alternative method, other than a full SPI controller, for
programming the device (see the AN-812 Application Note).
DON’T CARE
DON’T CAREDON’T CARE
DON’T CARE
SDIO
SCLK
CSB
t
S
t
DH
t
HI
t
CLK
t
LO
t
DS
t
H
R/W W1 W0 A12 A11 A10 A9 A8 A7
D5 D4 D3 D2 D1 D0
07029-068
Figure 69. Serial Timing Details
Table 16. Serial Timing Definitions
Parameter Minimum Timing (ns) Description
t
DS
5 Setup time between the data and the rising edge of SCLK
t
DH
2 Hold time between the data and the rising edge of SCLK
t
CLK
40 Period of the clock
t
S
5 Setup time between CSB and SCLK
t
H
2 Hold time between CSB and SCLK
t
HI
16 Minimum period that SCLK should be in a logic high state
t
LO
16 Minimum period that SCLK should be in a logic low state
t
EN_SDIO
10
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 69)
t
DIS_SDIO
10
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 69)