Datasheet
AD9272
Rev. C | Page 12 of 44
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LI-F
LG-F
LO-F
LI-G
LG-G
LO-G
AVDD1
CLK–
NOTES
1. THE EXPOSED PAD SHOULD BE TIED TO A QUIET ANALOG GROUND.
CLK+
AVDD2
AVDD1
AVDD1
AVDD1
LI-E
LG-E
AVDD2
AVDD2
LI-H
LG-H
LO-H
AVDD2
AVDD1
LOSW-F
LOSW-G
LOSW-H
07029-005
AD9272
TOP VIEW
(Not to Scale)
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AVDD1
74
75
PDWN
73
STBY
72
DRVDD
71
DOUTA+
70
DOUTA–
69
DOUTB+
68
DOUTB–
67
DOUTC+
66
DOUTC–
65
DOUTD+
64
DOUTD–
63
FCO+
62
FCO–
61
DCO+
60
DCO–
59
DOUTE+
58
DOUTE–
57
DOUTF+
56
DOUTF–
55
DOUTG+
54
DOUTG–
53
DOUTH+
52
DOUTH–
51
DRVDD
AVDD1
LI-A
LG-A
LOSW-A
LI-B
LG-B
LO-B
AVDD1
SDIO
SCLK
CSB
AVDD2
AVDD2
LI-C
LG-C
LO-C
AVDD1
AVDD2
LI-D
LG-D
AVDD1
AVDD2
LO-A
LOSW-B
LOSW-C
LOSW-
D
LO-D
CWD0–
CWD0+
CWD1–
CWD1+
CWD2–
CWD2+
CWD3–
CWD3+
AVDD2
GAIN–
GAIN+
VREF
RBIAS
CWD5–
CWD5+
CWD4–
CWD4+
CWD6–
CWD6+
CWD7–
CWD7+
LO-E
LOSW-E
Figure 4. TQFP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Name Description
0 GND Ground (exposed paddle should be tied to a quiet analog ground)
4, 10, 16, 22, 25, 50,
54, 60, 66, 72
AVDD1 1.8 V Analog Supply
3, 9, 15, 21, 55, 61,
67, 73, 86
AVDD2 3.0 V Analog Supply
26, 47 DRVDD 1.8 V Digital Output Driver Supply
1 LI-E LNA Analog Input for Channel E
2 LG-E LNA Ground for Channel E
5 LO-F LNA Analog Inverted Output for Channel F
6 LOSW-F LNA Analog Switched Output for Channel F
7 LI-F LNA Analog Input for Channel F
8 LG-F LNA Ground for Channel F
11 LO-G LNA Analog Inverted Output for Channel G
12 LOSW-G LNA Analog Switched Output for Channel G
13 LI-G LNA Analog Input for Channel G
14 LG-G LNA Ground for Channel G
17 LO-H LNA Analog Inverted Output for Channel H
18 LOSW-H LNA Analog Switched Output for Channel H
19 LI-H LNA Analog Input for Channel H