Datasheet

AD9271
Rev. B | Page 8 of 60
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 mV p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless
otherwise noted.
Table 3.
Parameter
1
Temp Min Typ Max Unit
CLOCK
2
Maximum Clock Rate Full 50 MSPS
Minimum Clock Rate Full 10 MSPS
Clock Pulse Width High (t
EH
) Full 10.0 ns
Clock Pulse Width Low (t
EL
) Full 10.0 ns
OUTPUT PARAMETERS
2, 3
Propagation Delay (t
PD
) Full 1.5 2.3 3.1 ns
Rise Time (t
R
) (20% to 80%) Full 300 ps
Fall Time (t
F
) (20% to 80%) Full 300 ps
FCO Propagation Delay (t
FCO
) Full 1.5 2.3 3.1 ns
DCO Propagation Delay (t
CPD
)
4
Full
t
FCO
+
(t
SAMPLE
/24)
ns
DCO to Data Delay (t
DATA
)
4
Full (t
SAMPLE
/24) − 300 (t
SAMPLE
/24) (t
SAMPLE
/24) + 300 ps
DCO to FCO Delay (t
FRAME
)
4
Full (t
SAMPLE
/24) − 300 (t
SAMPLE
/24) (t
SAMPLE
/24) + 300 ps
Data-to-Data Skew (t
DATA-MAX
− t
DATA-MIN
) Full ±50 ±200 ps
Wake-Up Time (Standby), V
GAIN
= 0.5 V 25°C 1 µs
Wake-Up Time (Power-Down) 25°C 1 ms
Pipeline Latency Full 8
Clock
cycles
APERTURE
Aperture Uncertainty (Jitter) 25°C <1 ps rms
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
Can be adjusted via the SPI interface.
3
Measurements were made using a part soldered to FR-4 material.
4
t
SAMPLE
/24 is based on the number of bits divided by 2, because the delays are based on half duty cycles.