Datasheet
AD9271
Rev. B | Page 48 of 60
06304-089
CLK
CLKB
GND
GND_PAD
OUT0
OUT0B
OUT1
OUT1B
RSET
S0
S1
S10
S2
S3
S4
S5
S6
S7
S8
S9
SYNCB
VREF
VS
SIGNAL=DNC;27,28
SIGN AL=AVDD_3.3V;4,17,20,21,24,26,29,3 0
+IN 1
+IN2
-IN1
-IN2
OUT1
OUT2
V+
V-
AD822A RT Z
+
-
+
-
GN DT
C
OU
VC
TRI -
STAT E
AOUT
OPTIONAL CONNECTIO N
TO AD8339 EVAL BOARD
AOUT
OPTIONAL CLOCK DRIVE CIRCUI T
LVDSOUTPUT
CLIPSINEOUT(DEFAULT)
LVPECLOUTPUT
AD9515Pin-strapsettings
W DOPPLER CIRCUITR Y
ENABLE
DISABLE
C
ENC
ENC
4
3
VFAC3
43
61
25
T402
ADTT4-1T+
1
2
H-L-50MHZ
OSC401
3
5
2
6
1
7
8
4
U402
3
2
1
CR401
HSMS-2812
2
3
31
33
23
22
19
18
32
25
16
7
15
14
13
12
11
10
9
8
5
6
1
U401
AD9515BCPZ
1
2
L408
560U H
2
1
560UH
L40 7
2
1
560U H
L406
1
2
L405
560U H
2
1
560U H
L402
1
2
L40 1
560UH
2
1
560U H
L403
1
2
L404
560U H
127
R448
R447
127
AVDD_3.3V
R436
0
R424
0-DN P 0
R425
R427
0
0-DN P
R432
0-DN P
R426
R452
0
0
R466
0-DN P
R406
R402
10K
C409
0.1UF
0
R417
6
14
25
3
T401
ADT1-1W+
750
R454
R422
100
S0
C401
0.1U F
OPT_CLK
OPT_CLK
0.1U F
C411
R415
0
100
R423
240
R421R420
240
C421
0.1U F
0.1U F
C419 C420
0.1U F
0.1UF
C422
R411
49.9-DNP
2
4
6
8
AVDD_3.3V
CLK
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
DNP
R412
AVDD_3.3V
10K
R410
DNP
R408 R409
DNP
OPT_CLK
R407
0-DN P
R446
0
0-DN P
R459
49.9
R404
R414
4.12K
AVDD_3.3V
0.1UF-DNP
C408
C407
0.1UF-DNP
C406
0.1UF-DNP
0.1UF-DNP
C405
7
5
3
1
P403
CLK
S10
1
E402
0
R403
CLK
R418
0
R416
0
C40 2
0.1UF
J402
R455
49.9
R450
0
AVDD_3.3V
10K
R401
1
2
3
J401
CWD5-
CWD5+
CWD4-
CWD4+
CWD1-
CWD1+
CWD0-
CWD0+
2
4
6
8
7
5
3
1
P405
AVDD_2.5V
+5V
R453
750
-5V
CWD2CWD1
0
R451
R449
0-DN P
R462
00
R460
CWD1
AVDD_3.3V
CWD2-
CWD2+
0-DN P
R465
49.9
R458
J403
CWD2
R461
0-DN P
R463
00
R464
R467
750
750
R468
AVDD_2.5V
AVDD_2.5V
R469
750
750
R470
AVDD_2.5V
1
3
5
7
8
6
4
2
P406
R405
0
0.1UF
C403
0.1UF
C410
1
E401
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
P402
AVDD_3.3V
ION
IOP
CWD3-
CWD3+
P401
CLK
R413
10K
OPT_CLK
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
C414
0.1U F0.1UF
C412 C413
0.1U F 0.1U F
C416C415
0.1U F 0.1UF
C417 C418
0.1U F
R428
0-DN P
R430
0-DN P
R434
0-DN P
R429
0
0
R431
0
R433
R435
0
0
R439
R441
0
0
R443
R445
0
0-DN P
R437
R438
0-DN P
0-DN P
R440
R442
0-DN P
0-DN P
R444
Figure 78. Evaluation Board Schematic, Clock and CW Doppler Circuitry