Datasheet

AD9271
Rev. B | Page 36 of 60
This interface is flexible enough to be controlled by either serial
PROMs or PIC mirocontrollers. This provides the user an
alternative method, other than a full SPI controller, to program
the device (see the AN-812 Application Note).
DON’T CARE
DON’T CAREDON’T CARE
DON’T CARE
SDIO
SCLK
CSB
t
S
t
DH
t
HI
t
CLK
t
LO
t
DS
t
H
R/W W1 W0 A12 A11 A10 A9 A8 A7
D5 D4 D3 D2 D1 D0
06304-068
Figure 71. Serial Timing Details
Table 14. Serial Timing Definitions
Parameter Minimum Timing (ns) Description
t
DS
5 Setup time between the data and the rising edge of SCLK
t
DH
2 Hold time between the data and the rising edge of SCLK
t
CLK
40 Period of the clock
t
S
5 Setup time between CSB and SCLK
t
H
2 Hold time between CSB and SCLK
t
HI
16 Minimum period that SCLK should be in a logic high state
t
LO
16 Minimum period that SCLK should be in a logic low state
t
EN_SDIO
10
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 71)
t
DIS_SDIO
10
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 71)