Datasheet
AD9271
Rev. B | Page 11 of 60
LI-F
LG-F
LO-F
LI-G
LG-G
LO-G
AVDD
CLK–
CLK+
AVDD
AVDD
AVDD
AVDD
LI-E
LG-E
AVDD
AVDD
LI-H
LG-H
LO-H
AVDD
AVDD
LOSW-F
LOSW-
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
G
LOSW-H
06304-005
AD9271
TOP VIEW
(Not to Scale)
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AVDD
74
75
PDWN
73
STBY
72
DRVDD
71
DOUTA+
70
DOUTA–
69
DOUTB+
68
DOUTB–
67
DOUTC+
66
DOUTC–
65
DOUTD+
64
DOUTD–
63
FCO+
62
FCO–
61
DCO+
60
DCO–
59
DOUTE+
58
DOUTE–
57
DOUTF+
56
DOUTF–
55
DOUTG+
54
DOUTG–
53
DOUTH+
52
DOUTH–
51
DRVDD
AVDD
LI-A
LG-A
LOSW-A
LI-B
LG-B
LO-B
AVDD
SDIO
SCLK
CSB
AVDD
AVDD
LI-C
LG-C
LO-C
AVDD
AVDD
LI-D
LG-D
AVDD
AVDD
LO-A
LOSW-B
LOSW-C
LOSW-D
LO-D
CWD0–
CWD0+
CWD1–
CW
D1+
CWD2–
CWD2+
CWVDD
GAIN–
GAIN+
RBIAS
SENSE
VREF
REFB
REFT
AVDD
CWD3–
CWD3+
CWD4–
CWD4+
CWD5–
CWD5+
LO-E
LOSW-E
Figure 4. 100-Lead TQFP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Name Description
0 GND Ground (exposed paddle should be tied to a quiet analog ground)
3, 4, 9, 10, 15,
16, 21, 22, 25,
50, 54, 55, 60,
61, 66, 67, 72,
73, 92
AVDD 1.8 V Analog Supply
26, 47 DRVDD 1.8 V Digital Output Driver Supply
84 CWVDD 3.3 V Analog Supply
1 LI-E LNA Analog Input for Channel E
2 LG-E LNA Ground for Channel E
5 LO-F LNA Analog Output for Channel F
6 LOSW-F LNA Analog Output Complement for Channel F
7 LI-F LNA Analog Input for Channel F
8 LG-F LNA Ground for Channel F
11 LO-G LNA Analog Output for Channel G
12 LOSW-G LNA Analog Output Complement for Channel G
13 LI-G LNA Analog Input for Channel G
14 LG-G LNA Ground for Channel G
17 LO-H LNA Analog Output for Channel H