Octal LNA/VGA/AAF/ADC and Crosspoint Switch AD9271 Each channel features a variable gain range of 30 dB, a fully differential signal path, an active input preamplifier termination, a maximum gain of up to 40 dB, and an ADC with a conversion rate of up to 50 MSPS. The channel is optimized for dynamic performance and low power in applications where a small package size is critical.
AD9271 TABLE OF CONTENTS Features .............................................................................................. 1 TGC Operation ........................................................................... 25 Applications ....................................................................................... 1 ADC ............................................................................................. 27 General Description ............................................................
AD9271 The AD9271 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. Fabricated in an advanced CMOS process, the AD9271 is available in a 16 mm × 16 mm, RoHS compliant, 100-lead TQFP. It is specified over the industrial temperature range of −40°C to +85°C. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate.
AD9271 SPECIFICATIONS AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 1.0 V internal ADC reference, fIN = 5 MHz, RS = 50 Ω, LNA gain = 15.6 dB (6), AAF LPF cutoff = 1/3 × fS, HPF cutoff = 700 kHz, full temperature, unless otherwise noted. Table 1.
AD9271 Parameter 1 Harmonic Distortion Second Harmonic fIN = 5 MHz at −7 dBFS Second Harmonic fIN = 5 MHz at −1 dBFS Third Harmonic fIN = 5 MHz at −7 dBFS Third Harmonic fIN = 5 MHz at −1 dBFS Two-Tone IMD3 (2 × F1 − F2) Distortion fIN1 = 5.0 MHz at −7 dBFS, fIN2 = 6.
AD9271 Parameter 1 POWER SUPPLY AVDD DRVDD CWVDD IAVDD IDRVDD Total Power Dissipation (Including Output Drivers) Conditions 1.7 1.7 3.0 Full-channel mode CW Doppler mode with four channels enabled Full-channel mode, no signal CW Doppler mode with four channels enabled Power-Down Dissipation Standby Power Dissipation Power Supply Rejection Ratio (PSRR) ADC RESOLUTION ADC REFERENCE Output Voltage Error (VREF = 1 V) Load Regulation @ 1.0 mA (VREF = 1 V) Input Resistance 1 2 3 Min AD9271-25 Typ 1.8 1.8 3.
AD9271 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 mV p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2.
AD9271 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 mV p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3.
AD9271 ADC TIMING DIAGRAMS N–1 AIN tA N tEH tEL CLK– CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA MSB N–9 D10 N–9 D9 N–9 D8 N–9 D7 N–9 D6 N–9 D5 N–9 D4 N–9 D3 N–9 D2 N–9 D1 N–9 D0 N–9 MSB N–8 D10 N–8 D7 N–9 D8 N–9 D9 N–9 D10 N–9 LSB N–8 D0 N–8 DOUTx+ 06304-002 DOUTx– Figure 2.
AD9271 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter ELECTRICAL AVDD DRVDD CWVDD GND AVDD Digital Outputs (DOUTx+, DOUTx−, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− LI-x LO-x LOSW-x CWDx−, CWDx+ SDIO, GAIN+, GAIN− PDWN, STBY, SCLK, CSB REFT, REFB, RBIAS VREF, SENSE ENVIRONMENTAL Operating Temperature Range (Ambient) Storage Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) With Respect To Rating GND GND GND GND DRVDD GND −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +3.
AD9271 76 LOSW-D 77 LO-D 78 CWD0– 79 CWD0+ 80 CWD1– 81 CWD1+ 82 CWD2– 83 CWD2+ 84 CWVDD 85 GAIN– 86 GAIN+ 87 RBIAS 88 SENSE 89 VREF 90 REFB 91 REFT 92 AVDD 93 CWD3– 94 CWD3+ 95 CWD4– 96 CWD4+ 97 CWD5– 98 CWD5+ 99 LO-E 100 LOSW-E PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR LI-D 74 LG-D AVDD 3 73 AVDD AVDD 4 72 AVDD 71 LO-C LOSW-F 6 70 LOSW-C LI-F 7 69 LI-C 68 LG-C 67 AVDD AVDD 10 66 AVDD LO-G 11 65 LO-B LOSW-G 12 64 LOSW-B LI-G 13 63
AD9271 Pin No.
AD9271 Pin No.
AD9271 EQUIVALENT CIRCUITS AVDD AVDD VCM 15kΩ 350Ω LI-x, LG-x SDIO 06304-008 06304-073 30kΩ Figure 8. Equivalent SDIO Input Circuit Figure 5. Equivalent LNA Input Circuit DRVDD AVDD V V DOUTx– DOUTx+ 06304-075 V V 06304-009 10Ω LO-x, LOSW-x DRGND Figure 9. Equivalent Digital Output Circuit Figure 6. Equivalent LNA Output Circuit 10Ω CLK+ 10kΩ 1.25V 10kΩ SCLK OR PDWN OR STBY 10Ω 30kΩ 06304-010 06304-007 CLK– 1kΩ Figure 7. Equivalent Clock Input Circuit Figure 10.
AD9271 AVDD 100Ω RBIAS AVDD 6kΩ 06304-014 06304-011 VREF Figure 14. Equivalent VREF Circuit Figure 11. Equivalent RBIAS Circuit AVDD 70kΩ 1kΩ CSB 50Ω 06304-012 06304-074 GAIN+ Figure 15. Equivalent GAIN+ Input Circuit Figure 12. Equivalent CSB Input Circuit 1kΩ SENSE 40kΩ +0.5V 06304-112 06304-013 GAIN– Figure 13. Equivalent SENSE Circuit Figure 16. Equivalent GAIN− Input Circuit 10Ω 06304-076 CWDx+, CWDx– Figure 17. Equivalent CWDx± Output Circuit Rev.
AD9271 TYPICAL PERFORMANCE CHARACTERISTICS fSAMPLE = 50 MSPS, fIN = 5 MHz, LPF = 1/3 × fSAMPLE, HPF = 700 kHz, LNA gain = 6×. 25 2.0 SAMPLE SIZE = 720 CHANNELS 1.5 PERCENT OF UNITS (%) ABSOLUTE ERROR (dB) 20 1.0 0.5 +85°C 0 +25°C –40°C –0.5 –1.0 15 10 06304-019 –2.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 06304-121 5 –1.5 0 1.0 –1.0 –0.8 VGAIN (V) –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 GAIN ERROR (dB) Figure 21. Gain Error Histogram with VGAIN = 0.9 V Figure 18.
AD9271 –131 1800000 –132 1400000 1200000 1000000 800000 600000 06304-022 400000 200000 0 –5 –4 –3 –2 –1 0 1 2 3 4 LNA GAIN = 8× –133 –134 –135 LNA GAIN = 6× –136 –137 –138 –139 –140 5 LNA GAIN = 5× 06304-021 NUMBER OF HITS 1600000 OUTPUT-REFERRED NOISE (dBFS/ Hz) 2000000 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VGAIN (V) CODES Figure 27. Short-Circuit, Output-Referred Noise vs. VGAIN Figure 24. Output-Referred Noise Histogram with VGAIN = 0.0 V 1200000 64.0 63.
AD9271 0 –50 –55 –3dB LINE –10 (1/3) × 50MSPS THIRD HARMONIC (dBFS) FUNDAMENTAL (dBFS) –5 –15 (1/3) × 40MSPS –20 –25 –30 (1/3) × 25MSPS VGAIN = 1V –60 –65 VGAIN = 0.5V –70 –75 VGAIN = 0.2V 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 –85 25.0 06304-029 –40 –80 06304-030 –35 2 4 6 8 FREQUENCY (MHz) 10 12 14 16 fIN (MHz) Figure 30. Antialiasing Filter (AAF) Pass-Band Response, No HPF Applied Figure 33. Third-Order Harmonic Distortion vs. Frequency, AIN = −0.
AD9271 0 0 –10 AIN1 = AIN2 = –7dBFS AIN1 = AIN2 = –7dBFS f1 = 5MHz f2 = 6MHz IMD2 = –70.59dBc IMD3 = –64.45dBc VGAIN = 1V –20 –20 AMPLITUDE (dBFS) IMD3 (dBFS) –30 –40 –50 8MHz AND 10.3MHz –60 –70 –40 –60 –80 –80 –90 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Figure 36. IMD3 vs. VGAIN f1 = 5MHz f2 = 6MHz –20 –40 –50 –60 –70 VGAIN = 0.5V VGAIN = 0V –90 06304-107 IMD3 (dBFS) –30 VGAIN = 1V –100 –110 –60 –55 –50 –45 –40 –35 –30 5 10 15 20 Figure 38.
AD9271 THEORY OF OPERATION following the TGC amplifier, and then beam forming is accomplished digitally. ULTRASOUND The primary application for the AD9271 is medical ultrasound. Figure 39 shows a simplified block diagram of an ultrasound system. A critical function of an ultrasound system is the time gain control (TGC) compensation for physiological signal attenuation. Because the attenuation of ultrasound signals is exponential with respect to distance (time), a linear-in-dB VGA is the optimal solution.
AD9271 RFB1 LO-x TO SWITCH ARRAY gm CFB RFB2 TRANSDUCER T/R SWITCH CS CDWx+ CDWx– LOSW-x LI-x ATTENUATOR –30dB TO 0dB LNA CSH CLG +24dB AAF LG-x 12-BIT PIPELINE ADC DOUTx– DOUTx+ AD9271 06304-071 GAIN– GAIN+ GAIN INTERPOLATOR SERIAL LVDS Figure 40. Simplified Block Diagram of a Single Channel CHANNEL OVERVIEW Each channel contains both a TGC signal path and a CW Doppler signal path. Common to both signal paths, the LNA provides useradjustable input impedance termination.
AD9271 Because the amplifier has a gain of 6× from its input to its differential output, it is important to note that the gain A/2 is the gain from Pin LI-x to Pin LO-x, and it is 6 dB less than the gain of the amplifier, or 9.6 dB (3×). The input resistance is reduced by an internal bias resistor of 15 kΩ in parallel with the source resistance connected to Pin LI-x, with Pin LG-x ac grounded. Equation 2 can be used to calculate the needed RFB for a desired RIN, even for higher values of RIN.
AD9271 16 INPUT OVERDRIVE Excellent overload behavior is of primary importance in ultrasound. Both the LNA and VGA have built-in overdrive protection and quickly recover after an overload event. 14 UNTERMINATED NOISE FIGURE (dB) 12 RESISTIVE TERMINATION 10 Input Overload Protection ACTIVE TERMINATION 8 As with any amplifier, voltage clamping prior to the inputs is highly recommended if the application is subject to high transient voltages. 6 4 100 1000 RS (Ω) Figure 44. Noise Figure vs.
AD9271 gain, and it defines a focal point within the body from which the location of the returning echo is derived. CW DOPPLER OPERATION Modern ultrasound machines used for medical applications employ a 2N binary array of receivers for beam forming, with typical array sizes of 16 or 32 receiver channels phase-shifted and summed together to extract coherent information.
AD9271 Crosspoint Switch The system gain is distributed as listed in Table 8. Each LNA is followed by a transconductance amp for V/I conversion. Currents can be routed to one of six pairs of differential outputs or to 12 single-ended outputs for summing. Each CWD output pin sinks 2.4 mA dc current, and the signal has a full-scale current of ±2 mA for each channel selected by the crosspoint switch. For example, if four channels were to be summed on one CWD output, the output would sink 9.
AD9271 0.450 slope is monotonic with respect to the control voltage and is stable with variations in process, temperature, and supply. LNA GAIN = 5x The X-AMP inputs are part of a 24 dB gain feedback amplifier that completes the VGA. Its bandwidth is about 70 MHz. The input stage is designed to reduce feedthrough to the output and to ensure excellent frequency response uniformity across the gain setting. 0.350 LNA GAIN = 6x 0.300 0.250 0.200 LNA GAIN = 8x 0.150 Gain Control 0.
AD9271 noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range. The output-referred noise is a flat 63 nV/√Hz over most of the gain range, because it is dominated by the fixed output-referred noise of the VGA. At the high end of the gain control range, the noise of the LNA and source prevail. The input-referred noise reaches its minimum value near the maximum gain control voltage, where the input-referred contribution of the VGA is miniscule.
AD9271 For optimum performance, the AD9271 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Figure 54 shows the preferred method for clocking the AD9271. A low jitter clock source, such as the Valpey Fisher oscillator VFAC3-BHL-50MHz, is converted from single-ended to differential using an RF transformer.
AD9271 190 In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter. IF undersampling applications are particularly sensitive to jitter (see Figure 59). 180 POWER/CHANNEL (mW) 170 The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9271.
AD9271 The AD9271 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option similar to the IEEE 1596.3 standard by using the SDIO pin or via the SPI. This LVDS standard can further reduce the overall power dissipation of the device by approximately 36 mW. See the SDIO Pin section or Table 15 for more information. The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 mA.
AD9271 400 600 EYE: ALL BITS 300 EYE: ALL BITS ULS: 2399/2399 ULS: 2396/2396 EYE DIAGRAM VOLTAGE (V) EYE DIAGRAM VOLTAGE (V) 400 200 100 0 –100 –200 200 0 –200 –400 –300 –1.0ns –0.5ns 0ns 0.5ns 1.0ns –600 1.5ns 25 20 20 TIE JITTER HISTOGRAM (Hits) 25 15 10 5 0 –200ps –100ps 0ps 100ps –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns 15 10 5 0 –200ps 200ps Figure 64. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Greater Than 24 Inches on Standard FR-4 –1.
AD9271 The format of the output data is offset binary by default. An example of the output coding format can be found in Table 9. To change the output data format to twos complement, see the Memory Map section. Table 9. Digital Output Coding Code 4095 2048 2047 0 (VIN+) − (VIN−), Input Span = 2 V p-p (V) +1.00 0.00 −0.000488 −1.00 Digital Output Offset Binary (D11 ... D0) 1111 1111 1111 1000 0000 0000 0111 1111 1111 0000 0000 0000 Data from each ADC is serialized and provided on a separate channel.
AD9271 When using the serial port interface (SPI), the DCO± phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO± timing, as shown in Figure 2, is 90° relative to the output data edge. An 8-, 10-, and 14-bit serial stream can also be initiated from the SPI. This allows the user to implement different serial streams to test the device’s compatibility with lower and higher resolution systems.
AD9271 Internal Reference Operation External Reference Operation A comparator within the AD9271 detects the potential at the SENSE pin and configures the reference. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 66), setting VREF to 1 V. The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics.
AD9271 SERIAL PORT INTERFACE (SPI) The AD9271 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. This offers the user added flexibility and customization depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, as documented in the Memory Map section.
AD9271 This interface is flexible enough to be controlled by either serial PROMs or PIC mirocontrollers. This provides the user an alternative method, other than a full SPI controller, to program the device (see the AN-812 Application Note). tDS tS tHI tCLK tDH tH tLO CSB SCLK DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE 06304-068 SDIO DON’T CARE DON’T CARE Figure 71. Serial Timing Details Table 14.
AD9271 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index and transfer register map (Address 0x04, Address 0x05, and Address 0xFF), and the ADC functions register map (Address 0x08 to Address 0x2D).
AD9271 Table 15. Memory Map Register 1 Addr. Bit 7 (Hex) Register Name (MSB) Chip Configuration Registers 00 chip_port_config 0 01 chip_id 02 chip_grade Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB first 1 = on 0 = off (default) Soft reset 1 = on 0 = off (default) 1 1 Soft reset 1 = on 0 = off (default) LSB first 1 = on 0 = off (default) Default Value Notes/ Comments 0 0x18 The nibbles should be mirrored so that LSB- or MSB-first mode is set correctly regardless of shift mode.
AD9271 Addr. (Hex) 0D Register Name test_io Bit 7 (MSB) Bit 6 User test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once 0F flex_channel_input 10 flex_offset 11 flex_gain Filter cutoff frequency control 0000 = 1.3 × 1/3 × fSAMPLE 0001 = 1.2 × 1/3 × fSAMPLE 0010 = 1.1 × 1/3 × fSAMPLE 0011 = 1.0 × 1/3 × fSAMPLE 0100 = 0.9 × 1/3 × fSAMPLE 0101 = 0.8 × 1/3 × fSAMPLE 0110 = 0.
AD9271 Addr.
AD9271 APPLICATIONS INFORMATION DESIGN GUIDELINES Exposed Paddle Thermal Heat Slug Recommendations Before starting design and layout of the AD9271 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins.
AD9271 EVALUATION BOARD The AD9271 evaluation board provides all the support circuitry required to operate the AD9271 in its various modes and configurations. The LNA is driven differentially through a transformer. Figure 73 shows the typical bench characterization setup used to evaluate the ac performance of the AD9271. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the signal chain.
AD9271 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS • PDWN: To enable the power-down feature, short P303 to the on position (AVDD) on the PDWN pin. The following is a list of the default and optional settings or modes allowed on the AD9271 Rev. B evaluation board. • STBY: To enable the standby feature, short P302 to the on position (AVDD) on the STBY pin.
AD9271 QUICK START PROCEDURE 4. The following is a list of the default and optional settings when using the AD9271 either on the evaluation board or at the system level design. In SPI Controller, select Controller Dialog from the Config menu. In the PROGRAM CONTROL box, ensure that Enable Auto Channel Update is selected and click OK. 5. In the Global tab of SPI Controller, find the DEVICE INDEX(4/5) box. In the ADC column, click S so that the adjustment in the next step applies to all channels. 6.
Rev. B | Page 45 of 60 J10 2 R10 4 0-DN P 0 R11 1 Figure 75. Evaluation Board Schematic, DUT Analog Input Circuits C11 8 0.1UF-DN P R11 2 0 R13 8 0 GND B 3 5 1 3 5 1 CT A CT B C11 7 0.1UF-DN P R13 7 0 R14 9 0 GND A R10 1 49.9-DN P 0 R10 2 R11 0 49.
Rev. B | Page 46 of 60 R22 2 0-DN P J20 2 0 R21 1 Figure 76. Evaluation Board Schematic, DUT Analog Input Circuits (Continued) C21 8 0.1UF-DN P R2 3 0 0 R2 3 8 0 GND F 3 3 1 1 CT E 5 CT F 5 C21 7 0.1UF-DN P R22 1 0 R20 3 0 GND E R20 1 49.9-DN P 0 R20 2 R2 1 0 49 .9-DN P AIN CHF R21 2 0-DN P J20 1 AIN CHE 4 2 6 4 2 6 R24 4 10K-DN P R20 4 10K-DN P AVD D ADT1-1WT + T20 2 R24 3 10K-DN P R24 2 10K-DN P AVD D ADT1-1WT + T20 1 0 R25 9 49.9 0 0 R26 2 R25 8 49.
AVDD CLK CLK AVDD LGH LIH LOSWH LO-H AVDD LGG LIG LOSWG LO-G AVDD LGF LIF LOSWF LO-F AVDD LGE LIE 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AVDD CLK+ CLK- AVDD AVDD LGH LIH LOSWH LO-H AVDD AVDD LGG LIG LOSWG LO-G AVDD AVDD LGF LIF LOSWF LO-F AVDD AVDD LGE LIE U301 101 PAD R301 10K VSENSE_DUT CWD4+ CWD5- C302 CWD5+ C304 0.1UF 100 4.7UF 97 CWD5- C303 0.1UF 26 AVDD_3.3V VREF_DUT 0.1UF C309 0.
5 7 CWD3- ION OPT_CLK OPT_CLK Figure 78. Evaluation Board Schematic, Clock and CW Doppler Circuitry 0 C411 0.1UF 0 R417 0 R418 R413 10K R410 10K AVDD_3.3V R411 49.9-DNP R409 DNP R466 0 CWD2 R450 0 0 R452 +IN 1 + AD822ARTZ + +IN2 5 -IN2 6 OUT2 7 V+ 8 750 R454 +5V R464 0 R461 0-DNP C422 0.1UF R463 0 CWD2 AOUT 5 3 2 1 SYNCB CLKB CLK U401 R414 4.12K AVDD_3.3V 22 23 SIGNAL=AVDD_3.
Figure 79. Evaluation Board Schematic, Power Supply and SPI Interface Circuitry 1UF C716 PWR_OUT 1UF C714 PWR_OUT 6 J501 4 2 3 3 INPUT U704 INPUT U707 10K R714 8 GND Y2 4 5 VCC Y1 6 U703 3 A2 2 OUTPUT 1 OUTPUT 4 ADP3339AKCZ-1.8-R L 2 OUTPUT 1 OUTPUT 4 4 4 Y2 4 5 VCC 2 GND Y1 6 1 A1 NC7WZ16P6X_N L U702 3 A2 ADP3339AKCZ-1.
AD9271 Digital Outputs FIFO5: DATA BUS 1 CONNECTOR P60 1 FIFO5: HS - SERIAL/SPI/AUX CONNECTOR 6469169-1 P60 2 GNDCD1 0 GNDCD1 0 60 60 C1 0 D1 0 40 50 C1 0 GNDCD 9 C9 D9 39 49 C9 GNDCD 8 C8 D8 38 48 C8 GNDCD 7 C7 D7 37 47 C7 GNDCD 6 C6 D6 36 46 C6 C5 D5 35 45 C5 C4 D4 34 44 C4 C3 D3 33 43 C3 C2 D2 C1 42 D1 R601-R610 Optional Output Terminations 32 29 C1 B1 0 100-DNP 20 DCO 10 A1 0 B9 100-DNP 19 CHA 7 9 A9 B8 100-DNP 18 CHB 6 8 A8 B
06304-084 AD9271 06304-083 Figure 81. Evaluation Board Layout, Top Side Figure 82. Evaluation Board Layout, Ground Plane (Layer 2) Rev.
06304-081 AD9271 06304-082 Figure 83. Evaluation Board Layout, Power Plane (Layer 3) Figure 84. Evaluation Board Layout, Power Plane (Layer 4) Rev.
06304-080 AD9271 06304-085 Figure 85. Evaluation Board Layout, Ground Plane (Layer 5) Figure 86. Evaluation Board Layout, Bottom Side Rev.
AD9271 Table 16. Evaluation Board Bill of Materials (BOM) 1 Item 1 Qty.
AD9271 Item 15 Qty. 2 Reference Designator J501, P403 Device Connector Package 8-pin 16 2 P302, P303 Connector 2-pin 17 2 P405, P406 Connector 8-pin 18 1 P511 Connector 3-pin 19 1 J401 Connector 3-pin 20 13 Connector SMA 21 2 J101, J102, J103, J104, J201, J202, J203, J204, J301, J402, J403, P401, P402 P601, P602 Connector HEADER 22 1 P701 Connector 0.
AD9271 Item 27 Qty. 3 Reference Designator R303, R422, R423 Device Resistor Package 402 Description 100 Ω, 1/16 W, 1% tol Manufacturer Panasonic KOA Yageo 28 7 R309, R319, R325, R326, R710, R712, R713 Resistor 402 1 kΩ, 1/16 W, 1% tol 29 1 R308 Resistor 402 470 kΩ, 1/16 W, 5% tol 30 2 R310, R336 Potentiometer 3-lead 31 1 R414 Resistor 402 10 kΩ, cermet trimmer potentiometer, 18-turn top adjust, 10%, 1/2 W 4.
AD9271 Item 42 Qty. 1 Reference Designator U402 Device IC Package SO8 43 1 U706 IC CP-8 44 2 U704, U707 IC SOT223-2 Description Dual current feedback op amp, SO8 500 mA, low noise, low dropout reg Regulator 45 1 U705 IC SOT223-2 Regulator 46 1 U702 IC SC88 47 1 U703 IC SC88 NC7WZ07, dual buffer, SC88 NC7WZ16P6X, UHS dual buffer, SC88 1 2 This BOM is RoHS compliant. May use suitable alternative. Rev.
AD9271 OUTLINE DIMENSIONS 0.75 0.60 0.45 16.00 BSC SQ 1.20 MAX 14.00 BSC SQ 100 1 76 75 76 75 100 1 PIN 1 EXPOSED PAD TOP VIEW (PINS DOWN) 9.50 SQ 0° MIN 1.05 1.00 0.95 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY 25 26 51 50 BOTTOM VIEW (PINS UP) 51 26 0.50 BSC LEAD PITCH VIEW A 25 50 0.27 0.22 0.
AD9271 NOTES Rev.
AD9271 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06304-0-5/09(B) Rev.
