Datasheet

AD9269
Rev. 0 | Page 22 of 40
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve thermal drift
characteristics. Figure 47 shows the typical drift characteristics
of the internal reference in 1.0 V mode.
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–40 –20 0 20 40 60 80
TEMPERATURE (°C)
V
REF
ERROR (mV)
V
REF
ERROR (mV)
0
8538-052
Figure 47. Typical V
REF
Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 32). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9269 sample clock
inputs, CLK+ and CLK−, with a differential signal. The signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased internally
(see Figure 48) and require no external bias.
0.9V
AVDD
2pF 2pF
CLK–CLK+
08538-016
Figure 48. Equivalent Clock Input Circuit
Clock Input Options
The AD9269 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter
is of the most concern, as described in the Jitter Considerations
section.
Figure 49 and Figure 50 show two preferred methods for clock-
ing the AD9269 (at rates up to 6× the specified sample rate when
using the internal clock divider function). A low jitter clock source
is converted from a single-ended signal to a differential signal
using either an RF balun or an RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 480 MHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary limit clock excursions into the AD9269 to approxi-
mately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9269 while pre-
serving the fast rise and fall times of the signal that are critical to
a low jitter performance.
0.1µF
0.1µF1nF
CLOCK
INPUT
1nF
50Ω
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
ADC
08538-018
Figure 49. Balun-Coupled Differential Clock (Up to 480 MHz)
0.1µF
0.1µF
0.1µF0.1µF
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT
50Ω
100Ω
CLK–
CLK+
ADC
Mini-Circuits
®
ADT1-1WT, 1:1 Z
XFMR
08538-017
Figure 50. Transformer-Coupled Differential Clock (Up to 200 MHz)