Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal LFCSP 64 VQ

16-Bit, 20/40/65/80 MSPS,

1.8 V Dual Analog-to-Digital Converter

AD9269

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

1.8 V analog supply operation

1.8 V to 3.3 V output supply

Integrated quadrature error correction (QEC)

SNR

77.6 dBFS at 9.7 MHz input

71 dBFS at 200 MHz input

SFDR

93 dBc at 9.7 MHz input

80 dBc at 200 MHz input

Low power

44 mW per channel at 20 MSPS

100 mW per channel at 80 MSPS

Differential input with 700 MHz bandwidth

On-chip voltage reference and sample-and-hold circuit

2 V p-p differential analog input

DNL = −0.5/+1.1 LSB

Serial port control options

Offset binary, gray code, or twos complement data format

Optional clock duty cycle stabilizer (DCS)

Integer 1-to-6 input clock divider

Data output multiplex option

Built-in selectable digital test pattern generation

Energy-saving power-down modes

Data clock output (DCO) with programmable clock and

data alignment

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers

GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA

I/Q demodulation systems

Smart antenna systems

Battery-powered instruments

Handheld scope meters

Portable medical imaging

Ultrasound

Radar/LIDAR

FUNCTIONAL BLOCK DIAGRAM

VIN+A

VIN–A

VREF

SENSE

VCM

RBIAS

VIN–B

VIN+B

ORA

D0A

D15A

DCOA

DRVDD

ORB

D15B

D0B

DCOB

SDI

GND

DD SCLK

SPI

QUADRATURE

ERROR

CORRECTION

PROGRAMMING DATA

MUX OPTION

PDWN DFSCLK+ CLK–

MODE

CONTROLS

DCS

DUTY CYCLE

STABILIZER

SYNC

DIVIDE

1TO 6

OEB

CSB

REF

SELECT

ADC

CMOS

OUTPUT BUFFER

ADC

CMOS

OUTPUT BUFFER

AD9269

08538-001

Figure 1.

PRODUCT HIGHLIGHTS

1. The AD9269 operates from a single 1.8 V analog power

supply and features a separate digital output driver supply

to accommodate 1.8 V to 3.3 V logic families.

2. The patented sample-and-hold circuit maintains excellent

performance for input frequencies up to 200 MHz and is

designed for low cost, low power, and ease of use.

3. An optional SPI selectable dc correction and quadrature

error correction (QEC) feature corrects for dc offset, gain,

and phase mismatches between the two channels.

4. A standard serial port interface (SPI) supports various

product features and functions, such as data output format-

ting, internal clock divider, power-down, DCO/data timing

and offset adjustments, and voltage reference modes.

5. The AD9269 is packaged in a 64-lead RoHS-compliant

LFCSP that is pin compatible with the AD9268 16-bit

ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC

the AD9231 12-bit ADC, the AD6659 12-bit baseband

diversity receiver, and the AD9204 10-bit ADC, enabling a

simple migration path between 10-bit and 16-bit converters

sampling from 20 MSPS to 125 MSPS.

Summary of content (40 pages)

PAGE 1
6-Bit, 20/40/65/80 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9269 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation 1.8 V to 3.3 V output supply Integrated quadrature error correction (QEC) SNR 77.6 dBFS at 9.7 MHz input 71 dBFS at 200 MHz input SFDR 93 dBc at 9.
PAGE 2
AD9269 TABLE OF CONTENTS Features .............................................................................................. 1 Clock Input Considerations ...................................................... 22 Applications ....................................................................................... 1 Power Dissipation and Standby Mode .................................... 24 Functional Block Diagram .............................................................. 1 Digital Outputs .......
PAGE 3
AD9269 GENERAL DESCRIPTION The AD9269 is a monolithic, dual-channel, 1.8 V supply, 16-bit, 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 16-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.
PAGE 4
AD9269 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error 1 Differential Nonlinearity (DNL) 2 Integral Nonlinearity (INL)2 MATCHING CHARACTERISTICS Offset Error Gain Error1 TEMPERATURE DRIFT Offset Error INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Load Regulation Error at 1.
PAGE 5
AD9269 Parameter POWER CONSUMPTION DC Input Sine Wave Input2 (DRVDD = 1.8 V) Sine Wave Input2 (DRVDD = 3.3 V) Standby Power 4 Power-Down Power Temp Min AD9269-20/AD9269-40 Typ Max Min AD9269-65 Typ Max AD9269-80 Typ Max Unit 200 224.6 mW mW Full Full 87.7/121.7 96.9/136.3 Full 114.4/165.7 235.6 279 mW Full Full 37/37 1.0 37 1.0 37 1.0 mW mW 102.0/142.3 170.7 191.2 Min 1 199.8 Measured with a 1.0 V external reference.
PAGE 6
AD9269 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz WORST SECOND OR THIRD HARMONIC fIN = 9.
PAGE 7
AD9269 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 3.
PAGE 8
AD9269 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 4.
PAGE 9
AD9269 TIMING SPECIFICATIONS Table 5.
PAGE 10
AD9269 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter AVDD to AGND DRVDD to AGND VIN+A, VIN+B, VIN−A, VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/DCS to AGND OEB to AGND PDWN to AGND D0x through D15x to AGND DCOx to AGND Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) Rating −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to AVDD + 0.
PAGE 11
AD9269 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD AVDD VIN+B VIN–B AVDD AVDD RBIAS VCM SENSE VREF AVDD AVDD VIN–A VIN+A AVDD AVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD9269 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PDWN OEB CSB SCLK/DFS SDIO/DCS ORA D15A (MSB) D14A D13A D12A D11A DRVDD D10A D9A D8A D7A NOTES 1.
PAGE 12
AD9269 Pin No. 49, 50, 53, 54, 59, 60, 63, 64 51, 52 55 56 57 58 61, 62 Mnemonic AVDD Description 1.8 V Analog Supply Pins. VIN+A, VIN−A VREF SENSE VCM RBIAS VIN−B, VIN+B Channel A Analog Inputs. Voltage Reference Input/Output. Reference Mode Selection. Analog Output Voltage at Midsupply. Sets the common mode of the analog inputs. Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. Channel B Analog Inputs. Rev.
PAGE 13
AD9269 TYPICAL PERFORMANCE CHARACTERISTICS AD9269-80 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 0 80MSPS 9.7MHz @ –1dBFS SNR = 76.8dB (77.8dBFS) SFDR = 94.3dBc –20 –40 –40 AMPLITUDE (dBFS) –60 –80 –100 –120 –60 –80 –100 –140 0 5 10 15 20 25 30 35 40 –140 0 5 10 15 FREQUENCY (MHz) 25 30 35 40 Figure 9. AD9269-80 Single-Tone FFT with fIN = 30.
PAGE 14
AD9269 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 120 100 SFDRFS SFDR (dBc) 90 100 70 SNR/SFDR (dBc/dBFS) SNR/SFDR (dBFS/dBc) 80 SNR (dBFS) 60 50 40 30 20 80 SNRFS SFDR 60 SNR 40 20 0 50 100 150 INPUT FREQUENCY (MHz) 200 0 –65 –60 08538-057 0 Figure 12. AD9269-80 SNR/SFDR vs.
PAGE 15
AD9269 AD9269-65 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 120 0 65MSPS 9.7MHz @ –1dBFS SNR = 76.9dB (77.9dBFS) SFDR = 95.9dBc SFDRFS 100 –40 SNR/SFDR (dBc/dBFS) –60 –80 –100 80 SNRFS SFDR 60 SNR 40 20 –140 0 5 10 15 20 25 30 08538-030 –120 0 –65 –60 –50 FREQUENCY (MHz) –10 0 Figure 21. AD9269-65 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz Figure 18.
PAGE 16
AD9269 AD9269-40 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 120 0 40MSPS 9.7MHz @ –1dBFS SNR = 76.9dB (77.9dBFS) SFDR = 95.1dBc SFDRFS 100 SNR/SFDR (dBFS/dBFS) –40 –60 –80 –100 SNRFS SFDR 60 SNR 40 20 –140 0 2 4 6 8 10 12 14 16 18 20 08538-028 –120 0 –65 –60 FREQUENCY (MHz) 0 40MSPS 30.6MHz @ –1dBFS SNR = 76.6dB (77.6dBFS) SFDR = 88.
PAGE 17
AD9269 AD9269-20 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 120 20MSPS 9.7MHz @ –1dBFS SNR = 76.9dB (77.9dBFS) SFDR = 95.6dBc SFDRFS 100 –40 SNR/SFDR (dBc/dBFS) –60 –80 –100 60 SFDR (dBc) 40 SNR (dBc) 20 –140 0 1 2 3 4 5 6 7 8 9 10 08538-024 –120 0 –90 FREQUENCY (MHz) 0 20MSPS 30.6MHz @ –1dBFS SNR = 76.7dB (77.7dBFS) SFDR = 90.
PAGE 18
AD9269 EQUIVALENT CIRCUITS DRVDD AVDD 08538-039 08538-042 VIN±x Figure 34. Equivalent Digital Output Circuit Figure 29. Equivalent Analog Input Circuit AVDD AVDD DRVDD 30kΩ 350Ω SDIO/DCS 375Ω RBIAS AND VCM 08538-041 08538-044 30kΩ Figure 35. Equivalent RBIAS, VCM Circuit Figure 30. Equivalent SDIO/DCS Input Circuit DRVDD DRVDD AVDD SCLK/DFS, SYNC, OEB, AND PDWN 350Ω 350Ω 30kΩ CSB 08538-043 08538-045 30kΩ Figure 31. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit Figure 36.
PAGE 19
AD9269 THEORY OF OPERATION In nondiversity applications, the AD9269 can be used as a baseband or direct downconversion receiver, in which one ADC is used for I input data and the other is used for Q input data. The AD9269 incorporates an optional, integrated dc correction and quadrature error correction block (QEC) that can correct for dc offset, gain, and phase mismatch between the two channels.
PAGE 20
AD9269 Input Common Mode driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. The analog inputs of the AD9269 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide a dc bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 39.
PAGE 21
AD9269 In any configuration, the value of Shunt Capacitor C is dependent on the input frequency and source impedance and may need to be reduced or removed. Table 9 displays the suggested values to set the RC network. However, these values are dependent on the input signal and should be used only as a starting guide. Table 9.
PAGE 22
AD9269 External Reference Operation Clock Input Options The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. Figure 47 shows the typical drift characteristics of the internal reference in 1.0 V mode. The AD9269 has a very flexible clock input structure. The clock input can be a CMOS, LVDS, LVPECL, or sine wave signal.
PAGE 23
AD9269 If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 51. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance. 0.1µF 0.1µF CLOCK INPUT Clock Duty Cycle CLK+ 0.1µF AD951x PECL DRIVER CLOCK INPUT 100Ω ADC 0.1µF 240Ω 50kΩ 08538-019 CLK– 50kΩ 240Ω Figure 51.
PAGE 24
AD9269 Jitter Considerations POWER DISSIPATION AND STANDBY MODE High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR from the low frequency SNR (SNRLF) at a given input frequency (fINPUT) due to jitter (tJRMS) can be calculated by As shown in Figure 56, the analog core power dissipated by the AD9269 is proportional to its sample rate.
PAGE 25
AD9269 The AD9269 is placed in power-down mode either by the SPI port or by asserting the PDWN pin high. In this state, the ADC typically dissipates 1 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD9269 to its normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage.
PAGE 26
AD9269 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9269 includes a built-in test feature that is designed to enable verification of the integrity of each channel as well as to facilitate board-level debugging. A built-in self-test (BIST) feature that verifies the integrity of the digital datapath of the AD9269 is included. Various output test options are also provided to place predictable values on the outputs of the AD9269.
PAGE 27
AD9269 CHANNEL/CHIP SYNCHRONIZATION The AD9269 has a SYNC input that offers the user flexible synchronization options for synchronizing sample clocks across multiple ADCs. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence.
PAGE 28
AD9269 DC AND QUADRATURE ERROR CORRECTION (QEC) Table 13 gives the minimum and maximum correction ranges of the algorithms. If the mismatches are greater than these ranges, an imperfect correction results. Table 13. QEC and DC Correction Range Parameter Gain Phase DC Minimum −1.1 dB −1.79 degrees −6 % Maximum +1.0 dB +1.79 degrees +6% 0 –15 –30 IMAGE DC OFFSET –45 –60 –75 2 –90 5 6 –105 4 3 –120 FREQUENCY (MHz) 08538-065 37.5M 30M 22.5M 15M 7.5M 0M –7.
PAGE 29
AD9269 SERIAL PORT INTERFACE (SPI) SPI functions are placed in high impedance mode. This mode turns on any secondary functions of the SPI function pins. The AD9269 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI provides added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port.
PAGE 30
AD9269 The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9269 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
PAGE 31
AD9269 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE DEFAULT VALUES Each row in the memory map register table (see Table 17) contains eight bit locations. The memory map is divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the device index and transfer registers (Address 0x05 and Address 0xFF); the program registers, including setup, control, and test (Address 0x08 to Address 0x2E); and the digital feature control registers (Address 0x100 to Address 0x11D).
PAGE 32
AD9269 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Addr.
PAGE 33
AD9269 Register Name Test mode (local) (MSB) Bit 7 Bit 6 User test mode (local) 00 = single 01 = alternate 10 = single once 11 = alternate once 0x0E BIST enable Open 0x10 8-bit device offset adjustment [7:0] (local) Offset adjust in LSBs from +127 to −128 (twos complement format) Output Open Output 00 = 3.3 V CMOS Output mux disable invert 10 = 1.
PAGE 34
AD9269 Register Name Features (MSB) Bit 7 Open Bit 6 Open Bit 5 Open Bit 4 Open Bit 3 Open Bit 2 Open Bit 1 Open 0x2E Output assign Open Open Open Open Open Open Open 0= ADC A 1= ADC B (local) Ch A = 0x00 Ch B = 0x01 Open Open Open Open Open Clock divider next sync only Run GCLK Clock divider sync enable Master sync enable 0x01 Open Disable SDIO pulldown Gain enable Force gain 0x88 Digital feature control 0x100 Sync control (global) Open Enable GCLK detect 0x101 USR2 0x11
PAGE 35
AD9269 QEC Phase Bandwidth Control (Register 0x113) Bits[7:5]—Open Bit 1—Open Bit 0—Disable SDIO Pull-Down This bit can be set high to disable the internal 30 kΩ pull-down on the SDIO pin, which can be used to limit the loading when many devices are connected to the SPI bus.
PAGE 36
AD9269 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9269 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements required for certain pins. Power and Ground Recommendations When connecting power to the AD9269, it is strongly recommended that two separate supplies be used. Use one 1.8 V supply for analog (AVDD), and use a separate 1.8 V to 3.
PAGE 37
AD9269 OUTLINE DIMENSIONS 0.60 MAX 9.00 BSC SQ 0.60 MAX 64 49 48 PIN 1 INDICATOR 1 PIN 1 INDICATOR 8.75 BSC SQ 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 SEATING PLANE 33 32 16 17 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 12° MAX 0.05 MAX 0.02 NOM 0.30 0.23 0.18 6.35 6.20 SQ 6.05 EXPOSED PAD (BOTTOM VIEW) 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
PAGE 38
AD9269 NOTES Rev.
PAGE 39
AD9269 NOTES Rev.