Datasheet

Data Sheet AD9266
Rev. A | Page 7 of 32
SWITCHING SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 4.
Parameter Temp
AD9266-20/AD9266-40 AD9266-65 AD9266-80
Unit Min Typ Max Min Typ Max Min Typ Max
CLOCK INPUT PARAMETERS
Input Clock Rate Full 80/320 520 625 MHz
Conversion Rate
1
Full 3 20/40 3 65 3 80 MSPS
CLK Period—Divide-by-1 Mode (t
CLK
) Full
50/25
15.38 12.5 ns
CLK Pulse Width High (t
CH
) 25.0/12.5 7.69 6.25 ns
Aperture Delay (t
A
) Full 1.0 1.0 1.0 ns
Aperture Uncertainty (Jitter, t
J
) Full 0.1 0.1 0.1 ps rms
DATA OUTPUT PARAMETERS
Data Propagation Delay (t
PD
) Full
1.84
3
3.90 1.84
3
3.90
1.84 3 3.90 ns
DCO Propagation Delay (t
DCO
) Full
1.86
3
4.04 1.86
3
4.04
1.86 3 4.04 ns
DCO to Data Skew (t
SKEW
) Full
−0.53
0.1
0.72 −0.53
0.1
0.72 −0.53
0.1 0.72 ns
Pipeline Delay (Latency)
Full
9
9
9
Cycles
Wake-Up Time
2
Full 350 350 350 µs
Standby Full 600/400 300 260 ns
OUT-OF-RANGE RECOVERY TIME Full 2 2 2 Cycles
1
Conversion rate is the clock rate after the CLK divider.
2
Wake-up time is dependent on the value of the decoupling capacitors.
08678-002
t
CLK
t
A
t
DCO
t
SKEW
t
SKEW
t
PD
V
IN
CLK+
CLK–
DCO
D1_D0
N – 1
N
N + 1
N + 2
N + 3
N + 5
N + 6
N + 7
N + 8
D1
N–9
D0
N–9
D1
N–8
D0
N–8
D1
N–7
D0
N–7
D1
N–6
D0
N–6
D1
N–5
D0
N–5
D1
N–4
D0
N–4
D15
N–9
D14
N–9
D15
N–8
D14
N–8
D15
N–7
D14
N–7
D15
N–6
D14
N–6
D15
N–5
D14
N–5
D15
N–4
D14
N–4
D15_D14
Figure 2. CMOS Output Data Timing