Datasheet

Data Sheet AD9266
Rev. A | Page 5 of 32
AC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 2.
Parameter
1
Temp
AD9266-20/AD9266-40 AD9266-65 AD9266-80
Unit Min Typ Max Min Typ Max Min Typ Max
SIGNAL-TO-NOISE RATIO (SNR)
f
IN
= 9.7 MHz 25°C 78.2 77.9 77.6 dBFS
f
IN
= 30.5 MHz 25°C 77.6 77.5 77.3 dBFS
Full 76.7 76.6 dBFS
f
IN
= 70 MHz 25°C 75.8/76.4 76.6 76.6 dBFS
Full 75.5 dBFS
f
IN
= 200 MHz 25°C 72.1 dBFS
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)
f
IN
= 9.7 MHz 25°C 78.0 77.7 77.4 dBFS
f
IN
= 30.5 MHz 25°C 77.5 77.3 77.1 dBFS
Full 76.2 76.2 dBFS
f
IN
= 70 MHz
25°C
75.7/76.3
76.5
76.6
dBFS
Full 75.5 dBFS
f
IN
= 200 MHz 25°C 69.4 dBFS
EFFECTIVE NUMBER OF BITS (ENOB)
f
IN
= 9.7 MHz 25°C 12.7 12.6 12.6 Bits
f
IN
= 30.5 MHz 25°C 12.6 12.5 12.5 Bits
f
IN
= 70 MHz 25°C 12.3/12.4 12.4 12.4 Bits
f
IN
= 200 MHz 25°C 11.2 Bits
WORST SECOND OR THIRD HARMONIC
f
IN
= 9.7 MHz 25°C −97 −96 −95 dBc
f
IN
= 30.5 MHz 25°C −96/−93 −94 −93 dBc
Full
−80
−80
dBc
f
IN
= 70 MHz 25°C −97/−95 −98 −95 dBc
Full −80 dBc
f
IN
= 200 MHz 25°C −80 dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
f
IN
= 9.7 MHz 25°C 95 95 94 dBc
f
IN
= 30.5 MHz 25°C 93 92 92 dBc
Full 80 80 dBc
f
IN
= 70 MHz 25°C 93 95 93 dBc
Full 80 dBc
f
IN
= 200 MHz 25°C 80 dBc
WORST OTHER (HARMONIC OR SPUR)
f
IN
= 9.7 MHz 25°C −102 −101 −99 dBc
f
IN
= 30.5 MHz 25°C −102 −101 −98 dBc
Full −89 −89 dBc
f
IN
= 70 MHz 25°C −101 −100 −98 dBc
Full −89 dBc
f
IN
= 200 MHz
25°C
−86
dBc
TWO-TONE SFDR
f
IN
= 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) 25°C 90 90 90 dBc
ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.