Datasheet
Data Sheet AD9266
Rev. A | Page 29 of 32
Addr
(Hex)
Register Name
Bit 7
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Comments
0x15 Output adjust
3.3 V DCO
drive strength
00 = 1 stripe (default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
1.8 V DCO
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes (default)
11 = 4 stripes
3.3 V data
drive strength
00 = 1 stripe (default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
1.8 V data drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes (default)
11 = 4 stripes
0x22
Determines CMOS
output drive
strength properties.
0x16 Output phase
DCO output
polarity
0 = normal
1 = inverted
Open Input clock phase adjust, Bits[2:0]
(Value is number of input clock
cycles of phase delay)
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
0x00
On devices that use
global clock divide,
determines which
phase of the divider
output is used to
supply the output
clock; internal
latching is
unaffected.
0x17 Output delay
Enable DCO
delay
Open
Enable
data
delay
Open DCO/data delay[2:0] (typical values)
000 = 0.56 ns
001 = 1.12 ns
010 = 1.68 ns
011 = 2.24 ns
100 = 2.80 ns
101 = 3.36 ns
110 = 3.92 ns
111 = 4.48 ns
0x00
Sets the fine
output delay of the
output clock but
does not change
internal timing.
(Typical values)
0x19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00
User-defined
pattern, 1 LSB.
0x1A USER_PATT1_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00
User-defined
pattern, 1 MSB.
0x1B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00
User-defined
pattern, 2 LSB.
0x1C USER_PATT2_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00
User-defined
pattern, 2 MSB.
0x2A OR/MODE select Open 0 = MODE
1 = OR
(default)
0x01
Selects I/O
functionality in
conjunction with
Address 0x08 for
MODE (input) or
OR (output) on
External Pin 23.
AD9266-Specific Customer SPI Control Register
0x10
1
USR2 Open
Enable
GCLK
detect
Run
GCLK
Open
Disable
SDIO pull-
down
0x08
Enables internal
oscillator for clock
rates of <5 MHz.