Datasheet

AD9266 Data Sheet
Rev. A | Page 24 of 32
OUTPUT TEST
The AD9266 includes various output test options to place
predictable values on the outputs of the AD9266.
OUTPUT TEST MODES
The output test options are described in Table 16 at Address 0x0D.
When an output test mode is enabled, the analog section of the
ADC is disconnected from the digital back end blocks and the
test pattern is run through the output formatting block. Some of
the test patterns are subject to output formatting, and some are
not. The PN generators from the PN sequence tests can be reset
by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be
performed with or without an analog signal (if present, the analog
signal is ignored), but they do require an encode clock. For more
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.